Abstract: The present invention relates to a salt recovery solution and to a process for separating a salt from an aqueous solution. The present disclosure also relates to a salt recovery solution and to its use to concentrate a salt or brine solution by recovering water therefrom. The salt recovery solution comprising at least two or more components independently selected from any combination of integers a), b), c) and d): where a) is a straight, branched or optionally substituted cyclic C4-C9 ether containing compound; b) is a straight chain or branched C3-C9 alkyl substituted by —OH; c) is a straight chain, branched or cyclic C4-C9 ketone or C4-C9 diketone; and d) is a straight chain or branched C3-C9 ester containing compound.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: The present disclosure relates to a solvent drying composition and processes therefor. The present disclosure more specifically relates to a solvent drying composition that in use releases water from a solvent mixture. The present disclosure also relates to a process for recovering a solvent drying composition, more specifically to a process for recovering a solvent drying composition used in an osmotic process.

Abstract: A conversion circuit includes a super source follower circuit configured to lower an impedance of a first node. A digital control circuit is configured to adjust a current at the first node based on a current through the super source follower. An output transistor has a gate configured to receive a first signal. A drain of the output transistor is coupled to a first node, and a source of the output transistor is configured to output an output current based on a voltage of the first signal.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: A conversion circuit includes a super source follower circuit configured to lower an impedance of a first node. A digital control circuit is configured to adjust a current at the first node based on a current through the super source follower. An output transistor has a gate configured to receive a first signal. A drain of the output transistor is coupled to a first node, and a source of the output transistor is configured to output an output current based on a voltage of the first signal.

Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.

Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.

Abstract: A high-speed SerDes transmitter which may reduce power supply introduced data dependent jitter. Instead of trying to make the output voltage of a power supply of a pre-driver constant, the output voltage of the power supply is returned to its normal level periodically, e.g., after each bit time to follow the data rate of an input data stream. A complementary pre-driver may be used to create a complementary data stream which may be at the same data rate as the input data rate. The complementary data stream may have a transition when there is no transition between two consecutive bits in the input data stream, but have no transition when there is a transition in the input data stream. As a result, there is a transition at the power supply during each bit time, and the power supply may be drawn back to its normal level during each bit time. Consequently, the power supply variation is periodic at the beat of the input data rate, and the power supply may have the same impact on each data bit.