Abstract: A backlight dimming circuit provides backlight by LED string; a local dimming module controls a grayscale level of the LED string; a current peak adjustment module adjusts a value of a peak output current flowing through the LED string; a drain of a first MOS transistor in a feedback module is coupled to a second terminal of the LED string, a source of which is grounded a first input terminal of an operational amplifier is coupled to a first terminal of the current peak adjustment module or a first terminal of the local dimming module, a second input terminal of the operational amplifier is coupled to the first terminal of the local dimming module or the first terminal of the current peak adjustment module, an output terminal of the operational amplifier is coupled to a gate of the first MOS transistor.

Abstract: Provided are a precise concentration generating device and a dust generation simulation method for dust particles, wherein the device includes a smoke cake particle generator and a water tank. The top of the smoke cake particle generator is equipped with a feeding port, and the bottom is equipped with a discharging port. The discharging port is connected to a material conveying pipeline, and the initial end of the material conveying pipeline is connected to a material conveying fan. The end of the material conveying pipeline is connected to the cyclone chamber of the cyclone cylinder, and a high-temperature heating tube is set at the bottom of the cyclone chamber. The top of the cyclone cylinder is equipped with a dust outlet, and the bottom of the cyclone cylinder is equipped with a slag discharge port.

Abstract: A dust suppression material with dual network reinforced structure and its preparation method is provided, which relates to the field of dust control technology. The material comprises by weight: 0.1-0.5 parts of sesbania gum, 0.1-0.9 parts of polyacrylamide, 0.1-0.5 parts of carboxymethyl cellulose, 0.06-0.14 parts of crosslinking agent, 0.11-0.19 parts of oxidant, 0.1-0.3 parts of water retaining agent, 0.2-1 parts of wetting agent, and the balance is distilled water. The dust suppressant with dual network reinforced structure produced by the present disclosure can effectively improve the hydrophilicity and adhesion of dust, form a dense protective film on the surface of dust, meet the requirements of dust suppressant adhesion and wettability for underground coal mining operations and outdoor coal storage filed, and will not cause secondary pollution to the environment.

Abstract: The present disclosure discloses a dust suppression material with a crosslinked network structure and its preparation method. The dust suppression material comprises: 16-20 parts of the cassava starch, 0.2-0.6 parts of the polyvinyl alcohol, 0.1-0.5 parts of the carboxymethyl cellulose, 0.1-0.5 parts of the crosslinking agent, 0.24-0.28 parts of the oxidizing agent, 0.4-0.48 parts of the catalyst, 1.8-2.6 parts of the gelatinizing agent, 0.1-0.3 parts of the water retaining agent, 0.8-1.2 parts of the wetting agent, and the balance is distilled water. The dust suppressant can wet and penetrate into the gaps of coal dust particles, and water molecules form hydrogen bonds with hydrophilic groups in the crosslinked network structure, firmly adsorbed on the network structure, thereby improving the water retention performance of the solidified layer.

Abstract: The present application provides a disconnection point detection method for single-wire series circuits, a single-wire series circuit, and a driver architecture. The method utilizes the existing parallel bus structure of the single-wire series circuit to detect disconnection points. Specifically, the position of the final short-circuit disconnection point is determined using the first correction command and the second address-assignment information, while the position of the final open-circuit disconnection point is determined using the second and third correction commands along with the third address-assignment information. The present application eliminates the need to add additional backup pins to each driver unit, thereby reducing the packaging cost of the single-wire series circuit and significantly lowering the packaging cost of the driver architecture.

Abstract: Disclosed are an aperture-adjustable mixed-flow nozzle and its atomization method. The nozzle includes a cylindrical shell with an airflow chamber and a mixed-flow chamber. The airflow chamber is connected to an air inlet, and the mixed-flow chamber is connected to a liquid inlet. An nozzle is provided at the bottom wall of the mixed-flow chamber on the cylindrical shell. The cylindrical shell allows airflow from the airflow chamber to enter the mixed-flow chamber through an adjusting shaft. A swirling flow path is disposed around the outer periphery of the adjusting shaft, and a gas path for connecting the airflow chamber and the mixed-flow chamber is disposed inside the adjusting shaft. By adjusting the nozzle aperture size, not only is the problem of nozzle blockage resolved, but it also allows for control of atomization effects and spray field conditions, making it more effective for complex dust-producing environments on-site.

Abstract: The present disclosure relates to the field of information identification. Disclosed are a method and terminal for identifying a barcode. The method comprises: obtaining an image of a barcode, and according to the calibration information of a preset calibration region, identifying the position of the calibration region in the image; identifying the position of an information code region in the image according to the position of the calibration region in the image, and a preset position relationship between the calibration region and the information code region in the image; and acquiring information on the position of the information code region in the image to obtain the information of the information code region.

Abstract: The present disclosure provides a method for controlling an amount of silicon added to ductile cast iron, a method for casting ductile cast iron, and a cast product, which relate to the technical fields of metallurgical and cast iron alloys. The method for controlling an amount of silicon added to ductile cast iron includes smelting ductile cast iron using scrap steel as a raw material. After the scrap steel is melted into molten iron, a copper alloy is added so that the molten iron has a copper equivalent of 0.8% to 1.0%, wherein the copper equivalent is controlled by formula (II). Then, ferrosilicon is added so that the content of silicon added to the molten iron satisfies formula (I).

Abstract: The present disclosure relates to the field of information identification. Disclosed are a method and terminal for identifying a barcode. The method comprises: obtaining an image of a barcode, and according to the calibration information of a preset calibration region, identifying the position of the calibration region in the image; identifying the position of an information code region in the image according to the position of the calibration region in the image, and a preset position relationship between the calibration region and the information code region in the image; and acquiring information on the position of the information code region in the image to obtain the information of the information code region.

Abstract: The present disclosure provides a method for controlling an amount of silicon added to ductile cast iron, a method for casting ductile cast iron, and a cast product, which relate to the technical fields of metallurgical and cast iron alloys. The method for controlling an amount of silicon added to ductile cast iron includes smelting ductile cast iron using scrap steel as a raw material. After the scrap steel is melted into molten iron, a copper alloy is added so that the molten iron has a copper equivalent of 0.8% to 1.0%, wherein the copper equivalent is controlled by formula (II). Then, ferrosilicon is added so that the content of silicon added to the molten iron satisfies formula (I).

Abstract: A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.

Abstract: Integrated circuits with memory elements are provided. Data may be loaded into the memory elements using write driver circuitry. The write driver circuitry may be provided with a fixed positive power supply voltage and an time-varying ground power supply voltage that is less than the positive power supply voltage. The time-varying ground power supply voltage may be generated using programmable power supply circuitry. The programmable power supply circuitry may include a pulse generation circuit and a configurable capacitive circuit. The pulse generation circuit may output a pulse signal to the capacitive circuit. In response to receiving the pulse signal, the capacitive circuit may push the time-varying ground power supply voltage to a negative value. The time-varying ground power supply voltage may be driven below zero volts for at least a portion of a write cycle to help improve write margins and increase memory yield.

Abstract: An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.

Abstract: An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.

Abstract: A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal.

Abstract: A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an embodiment of the present invention provides a memory circuit with a write control switch that has a voltage drop of substantially zero volts. In another aspect, an embodiment of the present invention provides a memory circuit with a write driver that uses a complementary metal oxide semiconductor (“CMOS”) inverter whose P-channel MOS (“PMOS”) transistor size is approximately 0.5 times its N-channel MOS (“NMOS”) transistor size. In yet another aspect, an embodiment of the present invention provides a memory circuit with a latch-type read sense amplifier.

Abstract: A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal.

Abstract: A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.