Patents by Inventor Haining An

Haining An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573748
    Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 10572390
    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 25, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Publication number: 20200056011
    Abstract: The application discloses cellulose ester compositions comprising two or more miscible blends of cellulose ester each comprising a plurality of propionyl substituents having tunable rheology and physical properties not achievable by any one of the cellulose esters alone. These cellulose ester compositions can be further processed, with or without other materials such as plasticizers, flame retardants, and blowing agents, and converted into articles. These cellulose ester compositions have higher modulus and have low to no butyryl/butyric acid content relative to cellulose acetate butyrate (“CAB”) cellulose ester compositions made from CABs having a butyryl content of greater than 30 wt %.
    Type: Application
    Filed: November 9, 2017
    Publication date: February 20, 2020
    Applicant: Eastman Chemical Company
    Inventors: Haining An, David Wayne Compton, Michael Eugene Donelson, Wesley Wayne McConnell, Jeffrey Todd Owens
  • Patent number: 10558580
    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 11, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Publication number: 20200044440
    Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.
    Type: Application
    Filed: March 22, 2019
    Publication date: February 6, 2020
    Inventors: John Jianhong ZHU, Xiangdong CHEN, Haining YANG, Kern RIM
  • Publication number: 20200043427
    Abstract: Aspects of the disclosure provide methods for adjusting backlight of devices and devices with adjustable backlight. In one example, a method for adjusting backlight of a device includes obtaining an ambient illuminance and adjusting a screen backlight brightness value of the device to be greater than a preset maximum brightness value when the obtained ambient illuminance is greater than an illuminance threshold. The method further includes detecting a temperature value of the device through a first temperature sensor installed in the device and adjusting the screen backlight brightness value of the device to be lower than or equal to the preset maximum brightness value when the temperature value of the device detected by the first temperature sensor is greater than a temperature threshold.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 6, 2020
    Applicant: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Guilin ZHONG, Guosheng LI, Haining HUANG
  • Publication number: 20200042366
    Abstract: This disclosure relates to an electronic device including a memory and at least one processor coupled to the memory. The at least one processor is configured to identify a device change event in a host operating system, wherein the host operating system includes a host namespace, switch from the host namespace to a container namespace of a container, and update the container with information based on the device change event.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Guruprasad Ganesh, Ahmed M. Azab, Rohan Bhutkar, Haining Chen, Ruowen Wang, Xun Chen, Donguk Seo, Kyoung-Joong Shin
  • Patent number: 10552352
    Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Vladislav Petkov, Radha Kumar Pulyala, Saurabh Garg, Haining Zhang
  • Patent number: 10551906
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Patent number: 10552055
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • Publication number: 20200032320
    Abstract: Methods for the high-throughput analysis of transgenic events are herein disclosed. The methods use libraries of sheared genomic DNA ligated to specialized adapters and pooled for sequence analysis and comparison to known genomic and insert sequence. The method finds use in detecting characterizing insertion site, transgene integrity, and transgene copy number.
    Type: Application
    Filed: October 10, 2019
    Publication date: January 30, 2020
    Applicant: PIONEER HI-BRED INTERNATIONAL, INC.
    Inventors: MARY BEATTY, KEVIN HAYES, JENNA HOFFMAN, HAINING LIN, GINA MARIE ZASTROW-HAYES
  • Publication number: 20200036303
    Abstract: Thermal electricity conversion based on the heat extracted from underground coal fires, comprising a coalfield fire area (1), coalfield drill holes (2), underground heat conduction pipelines (3) and a heat conduction container (4) which is provided with a pressure relief device (5) thereon and further comprises thermoelectric power generation chip sets (6) and a storage battery (7), wherein the thermoelectric power generation chip sets (6), having cold-side radiator pipes (8) provided on outer sides thereof, are provided on an outer side wall of the heat conduction container (4). The thermoelectric power generation chip sets in the invention are directly attached on the heat conduction container, so that the system is simple in structure without redundant components and high in heat conduction efficiency.
    Type: Application
    Filed: December 14, 2016
    Publication date: January 30, 2020
    Inventors: Fubao Zhou, Hetao Su, Bobo Shi, Haining Qi, Jinshi Li
  • Publication number: 20200035674
    Abstract: A fin field effect transistors (FinFET) array includes a first transistor having a fin and a first conductive gate on the fin. The FinFET array also includes a second transistor having another fin and a second conductive gate on the other fin. The FinFET array further includes a first dielectric material and a self-aligned dielectric spacer. The first dielectric material is between the first transistor and the second transistor and on at least a portion of sidewalls of each of the first conductive gate and the second conductive gate. The self-aligned dielectric spacer is on at least a portion of the sidewalls of each of the first conductive gate and the second conductive gate.
    Type: Application
    Filed: February 15, 2019
    Publication date: January 30, 2020
    Inventors: Ye LU, Haining YANG
  • Publication number: 20200020795
    Abstract: A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Junjing BAO, Ye LU, Haining YANG, Hyeokjin LIM
  • Publication number: 20200021383
    Abstract: We describe a wavelength division multiplexed (WDM) reconfigurable optical switch, the switch comprising: a set of arrays of optical beam connections, each comprising an array of optical outputs and having an optical input to receive a WDM input optical signal; a first diffractive element to demultiplexed said WDM input optical signal into a plurality of demultiplexed optical input beams, and to disperse said demultiplexed optical input beams spatially along a first axis; first relay optics between said set of arrays of optical beam connections and said first diffractive element; and a reconfigurable holographic array comprising a 2D array of reconfigurable sub-holograms defining sub-hologram rows and columns; wherein said arrays of said set of arrays are at least one dimensional arrays extending spatially in a direction parallel to said first axis and arranged in a column defining a second axis orthogonal to said first axis; wherein said sub-hologram rows are aligned along said first axis, and wherein said s
    Type: Application
    Filed: August 20, 2019
    Publication date: January 16, 2020
    Inventors: Brian Robertson, Daping Chu, Haining Yang, Peter John Wilkinson
  • Publication number: 20200012511
    Abstract: A method for operating an electronic device, the method including spawning a name space tool (NST) as part of a boot process of a host OS, wherein the NST is a process with a plurality of root privileges of the host OS. The method further includes spawning, by the NST, a container for a guest OS, wherein the container for the guest OS is mapped to a dedicated domain in the host OS, and dropping, by the NST, a root privilege of the host OS in response to spawning the container for the guest OS.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 9, 2020
    Inventors: Guruprasad Ganesh, Sudhi Herle, Ahmed M. Azab, Rohan Bhutkar, Ivan Getta, Xun Chen, Wenbo Shen, Ruowen Wang, Haining Chen, Khaled Elwazeer, Mengmeng Li, Peng Ning, Hyungseok Yu, Myungsu Cha, Kyungsun Lee, Se Young Choi, Yurak Choe, Yong Shin, Kyoung-Joong Shin, Donguk Seo, Junyong Choi
  • Publication number: 20190385049
    Abstract: Methods, systems, and devices for an artificial neural network are described. In one example, an artificial neuron in an artificial neural network may include a resistor coupled with an input line and configured to indicate a synaptic weight and a fuse coupled with the resistor. The artificial neuron may also include a selection component coupled with the fuse and configured to activate the fuse for programming the resistor, and a second selection component coupled with the resistor and an output line, the second selection component configured to select the resistor for a read operation.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Haining Yang, Periannan Chidambaram
  • Publication number: 20190377703
    Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 12, 2019
    Inventors: Vladislav Petkov, Saurabh Garg, Karan Sanghi, Haining Zhang
  • Patent number: 10500568
    Abstract: The present invention discloses a core-shell structure supported tungsten composite catalyst and a preparation method and use thereof. Most of the existing synthesis methods of the main ring of quinolone drugs have the defects of many synthesis steps, cumbersome operation, large amount of three wastes, higher costs and the like. The present invention prepares a magnetic separable core-shell supported tungsten composite catalyst, WO3/SiO2/Fe3O4, by preparing Fe3O4 colloid and SiO2/Fe3O4 composite nano-particles. This magnetic separable core-shell supported tungsten composite catalyst, WO3/SiO2/Fe3O4, is used to catalyze and synthesize quinolone compounds. The present invention provides an efficient preparation method of quinolone compounds using a catalyst which can be recovered by magnetic separation and recycled.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 10, 2019
    Assignees: Hangzhou Normal University, Zhejiang Benli Technology Co., Ltd.
    Inventors: Pengfei Zhang, Chao Shen, Xiaoling Li, Jun Xu, Haining Gu
  • Patent number: 10503412
    Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 10, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai