Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.

Abstract: Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.

Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.

Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.

Abstract: A method of wear leveling receives a write request. The write request indicates received data to be written to memory blocks. The method detects a system condition. Example system conditions include a random write condition, a garbage collection start condition, and/or a sequential write condition. Based on the system condition, the method determines whether the received data comprises hot data or cold data. Some embodiments use a write amplification value to determine the system condition. If the received data comprises hot data, the method writes the received data to a cold block. If the received data comprises cold data, the method writes the received data to a hot block.

Abstract: Data storage devices and systems include a non-volatile memory array including a plurality of non-volatile memory cells, a host interface for communicating with a host system, and a controller configured to receive data storage access commands from the host system over the host interface, determine an input/output (I/O) state of the data storage device based at least in part on the received data storage access commands, and execute a data management operation based at least in part on the I/O state of the data storage device.

Abstract: A device that provides garbage collection read throttling includes at least one processor that is configured to receive a request to perform a garbage collection read command on one of a plurality of flash memory circuits. The at least one processor is configured to determine whether garbage collection read throttling is enabled, such as when a garbage collection read throttling criterion is satisfied. The at least one processor is configured to buffer the garbage collection read command when garbage collection read throttling is enabled and perform the garbage collection read command when garbage collection read throttling is disabled. When the garbage collection read throttling is enabled and the garbage collection read command is buffered, the at least one processor is configured to perform the buffered garbage collection read command when garbage collection read throttling is subsequently disabled.

Abstract: A storage device may include a plurality of memory devices logically divided into a plurality of blocks and a controller. In some examples, the controller may be configured to determine a respective fullness percentage for each respective block of the plurality of blocks; determine the smallest fullness percentage for the plurality of respective fullness percentages; and responsive to determining that the smallest fullness percentage exceeds a predetermined threshold value, perform an action related to health of the storage device.

Abstract: A data storage device includes a nonvolatile solid-state memory comprising a plurality of blocks and a controller configured to maintain age data associated with each of a plurality of memory units, wherein each memory unit comprises one or more of the plurality of blocks, determine a capacity of the nonvolatile solid-state memory, and perform a wear leveling operation on a first memory unit of the plurality of memory units based at least in part on the age data associated with the first memory unit and the capacity of the nonvolatile solid-state memory.

Abstract: A method, system, and apparatus are provided for retiring computer memory blocks. Two overall schemes are provided for separating poorly functioning blocks from normally functioning blocks. In a first scheme, after data relocation is finished, firmware remembers the old physical memory block. As soon as the system writes to the old physical memory block with new data, firmware issues a read again and receives back a count of error bits. If the returned error bits are still high, then the system identifies the block as being weak and retires the block. In a second scheme, firmware tracks statistics for data relocates, block reads, activity timers, among other statistics. If some blocks have abnormal activities (e.g., too many data relocates, too many reads, etc.), then the system may identify the block as being weak and may retire the physical memory block.

Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.

Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Abstract: A data storage device includes a nonvolatile solid-state memory comprising a plurality of blocks and a controller configured to maintain age data associated with each of a plurality of memory units, wherein each memory unit comprises one or more of the plurality of blocks, determine a capacity of the nonvolatile solid-state memory, and perform a wear leveling operation on a first memory unit of the plurality of memory units based at least in part on the age data associated with the first memory unit and the capacity of the nonvolatile solid-state memory.

Abstract: Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.

Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.

Abstract: A method of wear leveling receives a write request. The write request indicates received data to be written to memory blocks. The method detects a system condition. Example system conditions include a random write condition, a garbage collection start condition, and/or a sequential write condition. Based on the system condition, the method determines whether the received data comprises hot data or cold data. Some embodiments use a write amplification value to determine the system condition. If the received data comprises hot data, the method writes the received data to a cold block. If the received data comprises cold data, the method writes the received data to a hot block.

Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.

Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.

Abstract: A method, system, and apparatus are provided for retiring computer memory blocks. Two overall schemes are provided for separating poorly functioning blocks from normally functioning blocks. In a first scheme, after data relocation is finished, firmware remembers the old physical memory block. As soon as the system writes to the old physical memory block with new data, firmware issues a read again and receives back a count of error bits. If the returned error bits are still high, then the system identifies the block as being weak and retires the block. In a second scheme, firmware tracks statistics for data relocates, block reads, activity timers, among other statistics. If some blocks have abnormal activities (e.g., too many data relocates, too many reads, etc.), then the system may identify the block as being weak and may retire the physical memory block.