Abstract: A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver.

Abstract: A method of calibrating data slicer-latches in a receiver to remove offset errors in the slicer-latches. A known voltage is applied to all but one of the inputs of the slicer-latch. The remaining input receives an offset cancelation voltage from a DAC is stepped upward from a minimum voltage until the slicer-latch output transitions by incrementing a codeword to the DAC and the codeword that resulted the transition is saved. Then the offset cancelation voltage is swept downward in steps from a maximum voltage until the slicer-latch output transitions and the codeword that caused the transition is averaged with the stored codeword. The average of the codewords is applied to the DAC to generate the offset cancelation voltage used during normal operation of the receiver.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.