Abstract: A display substrate includes a plurality of sub-pixels. The display substrate further includes: a base substrate; a plurality of temperature sensors disposed on a first side of the base substrate; and a light-shielding layer disposed on a peripheral side, a side proximate to the base substrate, and a side away from the base substrate, of a temperature sensor in the temperature sensors. The temperature sensor is configured to detect a temperature of at least one of the plurality of sub-pixels. The light-shielding layer is configured to shield light emitted to the temperature sensor.

Abstract: Disclosed are a dual-motor multi-gear hybrid transmission system and a vehicle. The dual-motor multi-gear hybrid transmission system includes an engine, a first motor, a second motor, a first clutch, a second clutch, a first planet row, a second planet row, a first input shaft, a second input shaft, a third input shaft and a brake assembly. The first input shaft is connected to the engine through the first clutch. The second input shaft is connected to the engine through the second clutch, and the second input shaft is sleeved outside the first input shaft. The first motor is connected to the engine. The second motor is connected to the first planet row through the third input shaft. The brake assembly is configured to brake the first planet row and/or the second planet row.

Abstract: The embodiments of the present disclosure provide a photoelectric detector, a method for manufacturing the photoelectric detector, and a detection device. The method for manufacturing the photoelectric detector includes: forming a thin film transistor array layer on a base substrate; forming an organic layer on a side of the thin film transistor array layer facing away from the base substrate; and patterning the organic layer to form a first via hole which enables a signal transmission layer in the thin film transistor array layer to be exposed; and depositing a photoelectric conversion device in the first via hole.

Abstract: Disclosed are a backlight module, a display panel, and a display device. The backlight module includes a module frame and at least one first conductive tip structure disposed inside the module frame, the first conductive tip structure includes a first conductive tip, the first conductive tip being in an exposed state of being exposed out from the module frame. The backlight module, according to a point discharge principle, preferentially performs discharging on static electricity through the conductive tip structure, to provide a novel antistatic backlight module.

Abstract: An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.

Abstract: Embodiments of the present disclosure relate to a three-dimensional touch sensing method, a three-dimensional display device and a wearable device. The three-dimensional touch sensing method, comprising: receiving an electron beam being perpendicularly incident to a preset plane on the preset plane, the electron beam having a preset emission intensity; obtaining a reception position and a reception intensity of the electron beam; determining a projection position of a touch position on the preset plane according to the reception position of the electron beam; and calculating a distance from the touch position to the preset plane according to the reception intensity of the electron beam and the preset emission intensity.

Abstract: An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises leading wires, the plurality of leading wires form a plurality of grooves in a fanout area of the array substrate, the plurality of grooves are filled with a filler, and the filler filled in the grooves has an upper surface which is flush with leading wires surrounding the grooves. The filler is made from an insulating and transparent material.

Abstract: An array substrate is disclosed herein, which includes a substrate, a plurality of signal lines, and conductive layer. The plurality of signal lines are disposed over the substrate, and have at least two signal lines insulated and staggered from one another to thereby form at least one signal line-staggered region at each site of staggering. It is configured such that a first zone formed by an orthographic projection of the at least one signal line-staggered region on the substrate is configured to have a gap with a second zone formed by an orthographic projection of the conductive layer on the substrate excluding the first zone. The array substrate can be a thin-film transistor array substrate, where the plurality of signal lines can include a common signal line and a plurality of gate lines, and the common signal line can be staggered with each gate line at a signal line-staggered region.

Abstract: The embodiments of the present disclosure provide a photoelectric detector, a method for manufacturing the photoelectric detector, and a detection device. The method for manufacturing the photoelectric detector includes: forming a thin film transistor array layer on a base substrate; forming an organic layer on a side of the thin film transistor array layer facing away from the base substrate; and patterning the organic layer to form a first via hole which enables a signal transmission layer in the thin film transistor array layer to be exposed; and depositing a photoelectric conversion device in the first via hole.

Abstract: An array substrate includes a substrate, a first signal line and a second signal line on the substrate, an insulating layer covering the first signal line and the second signal line, and a groove penetrating through the insulating layer. The first signal line and the second signal line are arranged in a same layer and separated from each other. The groove is between the first signal line and the second signal line.

Abstract: The present application provides an array electrode, which comprises: a plurality of gate lines, a plurality of data lines and a plurality of pixel units arranged in an array, wherein each pixel unit comprises a plate electrode, a slit electrode, and an insulating layer disposed between the plate electrode and the slit electrode. The slit electrode includes a plurality of electrode strips, with slits being formed between adjacent electrode strips, and an electrode strip that at least partially overlaps a projection of the data line on the array substrate being disconnected from other electrode strips. The present application also proposes a display device comprising said array substrate and a method for manufacturing said array substrate.

Abstract: An array substrate, a manufacturing method thereof, and a touch display device are provided in the embodiments of the present invention. The array substrate includes: a common electrode layer including a plurality of self-capacitance electrodes distributed in an array; a drive circuit; and a plurality of pixel units distributed in an array. N self-capacitance electrodes located in a same column constitute an electrode column, each electrode column corresponding to M columns of pixel units. The N self-capacitance electrodes located in the same column are connected with the drive circuit via N touch leads arranged within different columns of pixel units. Among the M columns of pixel units, M?N columns of pixel units provided with no touch leads are provided with dummy leads connected with the drive circuit, and the drive circuit is used to input a common voltage signal into the dummy leads and the touch leads.

Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.

Abstract: An array substrate is disclosed herein, which includes a substrate, a plurality of signal lines, and conductive layer. The plurality of signal lines are disposed over the substrate, and have at least two signal lines insulated and staggered from one another to thereby form at least one signal line-staggered region at each site of staggering. It is configured such that a first zone formed by an orthographic projection of the at least one signal line-staggered region on the substrate is configured to have a gap with a second zone formed by an orthographic projection of the conductive layer on the substrate excluding the first zone. The array substrate can be a thin-film transistor array substrate, where the plurality of signal lines can include a common signal line and a plurality of gate lines, and the common signal line can be staggered with each gate line at a signal line-staggered region.

Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.

Abstract: An array substrate, a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a base substrate, and a gate layer, an active layer, a data line layer, a resin layer, a first transparent electrode and a second transparent electrode disposed on the base substrate, the first transparent electrode and the second transparent electrode being insulated from each other. The second transparent electrode is extended below the resin layer via a through hole of the resin layer, the first transparent electrode includes a hollowed-out region; and an orthographic projection of the through hole of the resin layer on the base substrate falls within an orthographic projection of the hollowed-out region of the first transparent electrode on the base substrate.

Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.

Abstract: An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.

Abstract: The present disclosure discloses an array substrate, a display panel and a display device. The array substrate includes gate regions, gate lines, data lines, pixel electrodes and common electrode lines. The common electrode lines and the gate lines have the same extension direction, the pixel electrodes are located in regions defined by adjacent gate lines and adjacent data lines, the gate lines traverse the gate regions in the extension direction that are located in the same row as the gate lines, and the pixel electrodes have a gap from the gate lines at ends thereof closer to the gate lines. As such, a portion of the gate region that extends to the pixel region has a reduced area and hence a reduced edge length. This way, during the cleaning of the active layer after formation, less active layer metal may remain at the edges of the gate region. Thereby, the array substrate fabrication process is improved, and a product yield rate of the array substrate is increased.