Patents by Inventor Haitao Mei
Haitao Mei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9906230Abstract: The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.Type: GrantFiled: April 14, 2016Date of Patent: February 27, 2018Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Dmitry Petrov, Haitao Mei
-
Publication number: 20170302284Abstract: The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.Type: ApplicationFiled: April 14, 2016Publication date: October 19, 2017Inventors: Dmitry PETROV, Haitao MEI
-
Patent number: 8217693Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: GrantFiled: February 14, 2011Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
-
Publication number: 20110156806Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: ApplicationFiled: February 14, 2011Publication date: June 30, 2011Inventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
-
Patent number: 7902888Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: GrantFiled: May 15, 2008Date of Patent: March 8, 2011Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
-
Patent number: 7619460Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.Type: GrantFiled: January 23, 2008Date of Patent: November 17, 2009Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Mirza Baig
-
Patent number: 7580497Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.Type: GrantFiled: June 29, 2005Date of Patent: August 25, 2009Assignee: Altera CorporationInventors: Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
-
Patent number: 7528635Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: GrantFiled: February 23, 2007Date of Patent: May 5, 2009Assignee: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
-
Patent number: 7486752Abstract: A received clock signal is aligned (“eye centered”) with a received data signal by recovering a separate clock from the data signal and comparing and aligning the received clock with the recovered clock by delaying one or both of the received clock and the received data as necessary. After the necessary delays are set, the comparison/alignment circuitry can be turned off, until the next time alignment is necessary, to conserve power. In a multiple channel system, any combination of each received data channel, the received clock, or individual branches of the received clock in each channel can be delayed as necessary. Each channel can have its own comparison/alignment circuitry so that all channels can be aligned simultaneously, or re-usable circuitry can be provided for connection sequentially to each channel where sequential alignment of the channels is fast enough.Type: GrantFiled: December 17, 2003Date of Patent: February 3, 2009Assignee: Altera CorporationInventors: Tad Kwasniewski, Bill Bereza, Shoujun Wang, Mashkoor Baig, Haitao Mei
-
Patent number: 7453294Abstract: A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.Type: GrantFiled: June 28, 2005Date of Patent: November 18, 2008Assignee: Altera CorporationInventors: Shoujun Wang, Haitao Mei, Bill Bereza
-
Publication number: 20080197906Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.Type: ApplicationFiled: January 23, 2008Publication date: August 21, 2008Applicant: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William W. Bereza, Mirza M. Baig
-
Patent number: 7388443Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.Type: GrantFiled: April 25, 2006Date of Patent: June 17, 2008Assignee: Altera CorporationInventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
-
Patent number: 7385429Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: GrantFiled: May 31, 2005Date of Patent: June 10, 2008Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
-
Patent number: 7352229Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.Type: GrantFiled: July 10, 2006Date of Patent: April 1, 2008Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Mirza Baig
-
Publication number: 20070241795Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: ApplicationFiled: February 23, 2007Publication date: October 18, 2007Applicant: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
-
Patent number: 7239849Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.Type: GrantFiled: November 4, 2003Date of Patent: July 3, 2007Assignee: Altera CorporationInventors: Bill Bereza, Mashkoor Baig, Shoujun Wang, Haitao Mei, Tad Kwasniewski
-
Patent number: 7224191Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.Type: GrantFiled: November 17, 2006Date of Patent: May 29, 2007Assignee: Altera CorporationInventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei
-
Patent number: 7196557Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: GrantFiled: January 13, 2004Date of Patent: March 27, 2007Assignee: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
-
Publication number: 20070002993Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.Type: ApplicationFiled: June 29, 2005Publication date: January 4, 2007Inventors: Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
-
Patent number: 7157944Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.Type: GrantFiled: April 27, 2004Date of Patent: January 2, 2007Assignee: Altera CorporationInventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei