Abstract: In one embodiment of the invention, a processor includes a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads. The processor also includes detection circuitry to detect speculation errors in the execution of the threads. In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program.

Abstract: A prioritized content addressable memory having an at most one hit property despite the presence of redundant values stored therein. Redundant values within the content addressable memory are prioritized prior to performing value matching. Value matching of input data is performed only against any unique values and any highest ranked redundant value stored in the content addressable memory.

Abstract: In one embodiment of the invention, a processor includes a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

Abstract: The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads. The processor also includes detection circuitry to detect speculation errors in the execution of the threads. In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program.

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer outside the execution pipeline to hold the instructions, and wherein instructions that are associated with speculation errors are replayed in the execution pipeline from the trace buffer. In another embodiment, the processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer outside the execution pipeline to hold instructions and results of the execution of the instructions, wherein at least some of the instructions are subject to an initial retirement following execution in the pipeline, but remain in the trace buffer until a final retirement.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads. The processor also includes detection circuitry to detect speculation errors in the execution of the threads. In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program.

Abstract: The method and apparatus are employed within a microprocessor capable of generating speculative memory accesses instructions. Certain instructions access memory locations containing speculatable information while others access memory locations containing non-speculatable information. Memory-type values indicating the speculatability or non-speculatability of memory locations are stored within a translation lookaside buffer. Prior to executing a speculative memory instruction, the microprocessor accesses the translation lookaside buffer to determine whether the memory location targeted by a memory instruction contains speculatable or non-speculatable information. Then, depending upon the memory-type value found in the translation lookaside buffer, execution of the speculative memory instruction is performed immediately or is deferred until the instruction is no longer speculative.

Abstract: A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

Abstract: A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

Abstract: The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

Abstract: A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.

Abstract: A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

Abstract: A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

Abstract: A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.

Abstract: A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.

Abstract: A page table walk is performed in response to a data translation lookaside buffer miss based on a speculative memory instruction. In the event of a data translation lookaside buffer miss, a page miss handler determines whether the memory micro-instruction causing the miss is a speculative or non-speculative micro-instruction. If non-speculative, the page miss handler performs a non-speculative page table walk. If the memory micro-instruction causing the miss is a speculative micro-instruction, the page miss handler initiates a speculative page table walk. While performing the speculative page table walk, the page miss handler determines whether page table memory accessed during the page table walk is speculateable or non-speculateable memory. If non-speculateable, the speculative page table walk is aborted. A micro-instruction assisted page table walk is performed whenever access or dirty bits must be set for the pages accessed in the page table walk.