Abstract: Methods and apparatus to provide unbounded transactional memory systems are described. In one embodiment, an operation corresponding to a software transactional memory (STM) access may be executed if a preceding hardware transactional memory (HTM) access operation fails.

Abstract: Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

Abstract: Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.

Abstract: Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery.

Abstract: A method and apparatus for executing a selective recovery after a branch misprediction is disclosed. In one embodiment, the instructions following the mispredicted branch point may be saved for selective re-execution in a buffer. Those instructions that wrote to physical registers between the mispredicted branch point and an exact convergence point, thereby causing false data dependencies, may be followed by corresponding move instructions to eliminate the false data dependencies. The instructions subsequent to the exact convergence point may then be selectively re-executed if subject to the previous false data dependencies.

Abstract: A method and apparatus for recycling wrong-path branch outcomes in a superscalar single-threaded processor is disclosed. In one embodiment, a branch recycling predictor may be used to determine whether a speculatively executed branch instruction's outcome, coming at the end of a wrong-path branch, may be a better prediction than that given by a traditional branch predictor. In one embodiment, the branch recycling predictor may correlate the previous wrong-path branch outcomes with the previous correct-path branch outcomes. The history of the traditional branch predictor may also be used. The branch recycling predictor may be used to choose between using the traditional branch predictor's prediction, or instead using the wrong-path branch outcome.

Abstract: A method and apparatus for reducing wrong path execution in a speculative multi-threaded processor is disclosed. In one embodiment, a wrong path predictor may be used to enhance the selection of the right path at a branch point. In one embodiment, the wrong path predictor may include a speculative processor to produce a speculative processor execution outcome, and a branch corrector to determine whether to trust the speculative processor execution outcome. The branch corrector may be used to choose between using the speculative execution, or, instead, overriding the speculative execution with the non-speculative branch prediction.

Abstract: A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.