Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.

Abstract: A liquid crystal display includes: an upper substrate and a lower substrate spaced apart from each other, forming a cell gap therebetween. A liquid crystal layer is disposed in the cell gap between the upper substrate and the lower substrate and has liquid crystal molecules. A common electrode is disposed on the lower substrate facing the liquid crystal layer. A passivation layer is disposed on the lower substrate and covers the common electrode. Multiple pixel electrodes are disposed on the passivation layer. A planar electrode is disposed on the upper substrate facing the liquid crystal layer, and is provided with a first biased voltage. The liquid crystal molecules of the liquid crystal layer are vertically aligned at a voltage-off state. In some cases, the upper substrate has a first anchoring energy W2 and the lower substrate has a second anchoring energy W2, and W2 is weaker than W1.

Abstract: Display devices and related methods involving patterned phase retarding are provided. A representative display device includes: a backlight unit, having a light source and a color conversion layer having an alignment direction, the light comprising a first light exhibiting a first upstream polarization ratio, a second light exhibiting a second upstream polarization ratio, and a third light exhibiting a third upstream polarization ratio; and a patterned phase retarder positioned to receive the light, having a plurality of half-wave regions to alter polarization of light passing therethrough, and a plurality of free regions to pass light without altering the polarization; wherein polarization ratio (PR) is defined by PR=(I??I?)/(I?+I?); and wherein the first upstream polarization ratio exhibits a first sign, and both the second upstream polarization ratio and the third upstream polarization ratio exhibit a second sign opposite the first sign.

Abstract: Liquid crystal display (LCD) systems and related methods with pixel elements driven at different frequencies are provided. A representative LCD system includes: a plurality of pixel elements arranged in an array, each of the plurality of pixel elements having a first sub-region and a second sub-region; a low-frequency driving circuit operative to drive each of the first sub-regions; and a high-frequency driving circuit operative to drive each of the second sub-regions at a driving frequency different than a driving frequency of the low-frequency driving circuits; wherein the first sub-regions exhibit a different size than the second sub-regions.

Abstract: Display devices and related methods involving patterned phase retarding are provided. A representative display device includes: a backlight unit, having a light source and a color conversion layer having an alignment direction, the light comprising a first light exhibiting a first upstream polarization ratio, a second light exhibiting a second upstream polarization ratio, and a third light exhibiting a third upstream polarization ratio; and a patterned phase retarder positioned to receive the light, having a plurality of half-wave regions to alter polarization of light passing therethrough, and a plurality of free regions to pass light without altering the polarization; wherein polarization ratio (PR) is defined by PR=(l??l?)/(l?+l?); and wherein the first upstream polarization ratio exhibits a first sign, and both the second upstream polarization ratio and the third upstream polarization ratio exhibit a second sign opposite the first sign.

Abstract: Liquid crystal display (LCD) systems and related methods with pixel elements driven at different frequencies are provided. A representative LCD system includes: a plurality of pixel elements arranged in an array, each of the plurality of pixel elements having a first sub-region and a second sub-region; a low-frequency driving circuit operative to drive each of the first sub-regions; and a high-frequency driving circuit operative to drive each of the second sub-regions at a driving frequency different than a driving frequency of the low-frequency driving circuits; wherein the first sub-regions exhibit a different size than the second sub-regions.