Patents by Inventor Haiying Fu

Haiying Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11543548
    Abstract: A mechanical-model based earthquake-induced landslide hazard assessment method in earthquake-prone mountainous area includes: obtaining the cohesion and internal friction angle through a geological map of the study area and a geotechnical physical parameter; obtaining simulated ground motions by combining a pulse-like ground motion effect model and a pulse-like ground motion response model; calculating slope permanent displacement according to the simulated ground motions, the cohesion, the internal friction angle and other parameters; obtaining a statistical relationship between the permanent displacement and a landslide probability according to permanent displacement data derived from historical earthquake-induced landslides and historical strong earthquake records; and predicting earthquake-induced landslide probability according to the slope permanent displacement and the statistical relationship between the permanent displacement and the landslide probability, and quantitatively evaluating earthquake-ind
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 3, 2023
    Assignee: SOUTHWEST JIAOTONG UNIVERSITY
    Inventors: Yingbin Zhang, Jing Liu, Haiying Fu, Qingdong Wang, Chenlin Xiang, Dejian Li, Jiangtao Wei, Yin Cheng, Zhiwang Chang, Pengcheng Yu
  • Publication number: 20210026027
    Abstract: A mechanical-model based earthquake-induced landslide hazard assessment method in earthquake-prone mountainous area includes: obtaining the cohesion and internal friction angle through a geological map of the study area and a geotechnical physical parameter; obtaining simulated ground motions by combining a pulse-like ground motion effect model and a pulse-like ground motion response model; calculating slope permanent displacement according to the simulated ground motions, the cohesion, the internal friction angle and other parameters; obtaining a statistical relationship between the permanent displacement and a landslide probability according to permanent displacement data derived from historical earthquake-induced landslides and historical strong earthquake records; and predicting earthquake-induced landslide probability according to the slope permanent displacement and the statistical relationship between the permanent displacement and the landslide probability, and quantitatively evaluating earthquake-ind
    Type: Application
    Filed: July 27, 2020
    Publication date: January 28, 2021
    Applicant: Southwest Jiaotong University
    Inventors: Yingbin ZHANG, Jing LIU, Haiying FU, Qingdong WANG, Chenlin XIANG, Dejian LI, Jiangtao WEI, Yin CHENG, Zhiwang CHANG, Pengcheng YU
  • Patent number: 10662545
    Abstract: Methods and apparatus for electroplating material onto a substrate are provided. In many cases the material is metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a porous ionically resistive plate positioned near the substrate, the plate having a plurality of interconnecting 3D channels and creating a cross flow manifold defined on the bottom by the plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through channels in the plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 26, 2020
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Patent number: 10508359
    Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Lee Brogan, Steven T. Mayer, Matthew Thorum, Joseph Richardson, David W. Porter, Haiying Fu
  • Publication number: 20180105949
    Abstract: Methods and apparatus for electroplating material onto a substrate are provided. In many cases the material is metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a porous ionically resistive plate positioned near the substrate, the plate having a plurality of interconnecting 3D channels and creating a cross flow manifold defined on the bottom by the plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through channels in the plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Application
    Filed: October 31, 2017
    Publication date: April 19, 2018
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Publication number: 20180030611
    Abstract: Apparatus and methods for electroplating metal onto substrates are disclosed. The electroplating apparatus comprise an electroplating cell and at least one oxidization device. The electroplating cell comprises a cathode chamber and an anode chamber separated by a porous barrier that allows metal cations to pass through but prevents organic particles from crossing. The oxidation device (ODD) is configured to oxidize cations of the metal to be electroplated onto the substrate, which cations are present in the anolyte during electroplating. In some embodiments, the ODD is implemented as a carbon anode that removes Cu(I) from the anolyte electrochemically. In other embodiments, the ODD is implemented as an oxygenation device (OGD) or an impressed current cathodic protection anode (ICCP anode), both of which increase oxygen concentration in anolyte solutions. Methods for efficient electroplating are also disclosed.
    Type: Application
    Filed: October 11, 2017
    Publication date: February 1, 2018
    Inventors: Tighe A. Spurlin, Charles Lorenzo Merrill, Ludan Huang, Matthew Sherman Thorum, Lee J. Brogan, James E. Duncan, Frederick Dean Wilmot, Robert Marshall Stowell, Steven T. Mayer, Haiying Fu, David W. Porter, Shantinath Ghongadi, Jonathan David Reid, Hyosang S. Lee, Mark J. Willey
  • Patent number: 9834852
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 5, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Patent number: 9816196
    Abstract: Apparatus and methods for electroplating metal onto substrates are disclosed. The electroplating apparatus comprise an electroplating cell and at least one oxidization device. The electroplating cell comprises a cathode chamber and an anode chamber separated by a porous barrier that allows metal cations to pass through but prevents organic particles from crossing. The oxidation device (ODD) is configured to oxidize cations of the metal to be electroplated onto the substrate, which cations are present in the anolyte during electroplating. In some embodiments, the ODD is implemented as a carbon anode that removes Cu(I) from the anolyte electrochemically. In other embodiments, the ODD is implemented as an oxygenation device (OGD) or an impressed current cathodic protection anode (ICCP anode), both of which increase oxygen concentration in anolyte solutions. Methods for efficient electroplating are also disclosed.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: November 14, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Tighe A. Spurlin, Charles L. Merrill, Ludan Huang, Matthew Thorum, Lee Brogan, James E. Duncan, Frederick D. Wilmot, Robert Marshall Stowell, Steven T. Mayer, Haiying Fu, David W. Porter, Shantinath Ghongadi, Jonathan D. Reid, Hyosang S. Lee, Mark J. Willey
  • Patent number: 9746427
    Abstract: The embodiments herein relate to methods and apparatus for detecting whether unwanted metallic deposits are present on a bottom of a substrate holder used in an electroplating apparatus. The presence of such unwanted deposits is harmful to electroplating processes because the deposits scavenge current that is intended to cause electroplating on a substrate. When such current scavenging occurs, the electroplating results on the substrates are poor. For instance, features positioned near the edge of a substrate are likely to plate to an insufficient thickness. Further, where such current scavenging is great, the overall thickness of the material plated on the substrate may be too thin. As such, there is a need to detect when such unwanted deposits are present, such that plating under these poor conditions may be avoided. This detection will help preserve costly wafers.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 29, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Haiying Fu, Thomas Anand Ponnuswamy, Bryan L. Buckalew
  • Publication number: 20170241041
    Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventors: Lee Brogan, Steven T. Mayer, Matthew Thorum, Joseph Richardson, David W. Porter, Haiying Fu
  • Patent number: 9689083
    Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: June 27, 2017
    Assignee: Lam Research Corporation
    Inventors: Lee Brogan, Steven T. Mayer, Matthew Thorum, Joseph Richardson, David W. Porter, Haiying Fu
  • Publication number: 20170029973
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 2, 2017
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Patent number: 9523155
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 20, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Publication number: 20150157610
    Abstract: A pharmaceutical composition which comprises, as an active ingredient, a liposome encapsulating an immunosuppressant such as FK506, FTY720 and cyclosporin A is effective in the treatment of cardiovascular inflammatory diseases such as my ocardial infarction, myocarditis and vasculitis syndrome, allows the immunosuppressant at a low dose to produce stronger effects than those of the same dose of the immunosuppressant used alone, and causes fewer side effects.
    Type: Application
    Filed: May 23, 2013
    Publication date: June 11, 2015
    Inventors: Tetsuo Minamino, Issei Komuro, Takashi Matsuzaki, Naoto Oku, Tomohiro Asai, Haiying Fu
  • Publication number: 20140367279
    Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.
    Type: Application
    Filed: May 12, 2014
    Publication date: December 18, 2014
    Applicant: Lam Research Corporation
    Inventors: Lee Brogan, Steven T. Mayer, Matthew Thorum, Joseph Richardson, David W. Porter, Haiying Fu
  • Publication number: 20140230855
    Abstract: The embodiments herein relate to methods and apparatus for detecting whether unwanted metallic deposits are present on a bottom of a substrate holder used in an electroplating apparatus. The presence of such unwanted deposits is harmful to electroplating processes because the deposits scavenge current that is intended to cause electroplating on a substrate. When such current scavenging occurs, the electroplating results on the substrates are poor. For instance, features positioned near the edge of a substrate are likely to plate to an insufficient thickness. Further, where such current scavenging is great, the overall thickness of the material plated on the substrate may be too thin. As such, there is a need to detect when such unwanted deposits are present, such that plating under these poor conditions may be avoided. This detection will help preserve costly wafers.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 21, 2014
    Inventors: Steven T. Mayer, Haiying Fu, Thomas Anand Ponnuswamy, Bryan L. Buckalew
  • Publication number: 20140183049
    Abstract: The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.
    Type: Application
    Filed: December 11, 2013
    Publication date: July 3, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Bryan L. Buckalew, Haiying Fu, Thomas Ponnuswamy, Hilton Diaz Camilo, Robert Rash, David W. Porter
  • Patent number: D964573
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 20, 2022
    Inventor: Haiying Fu
  • Patent number: D967444
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: October 18, 2022
    Inventor: Haiying Fu
  • Patent number: D977118
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 31, 2023
    Inventor: Haiying Fu