Abstract: The present application discloses a method for rapidly identifying the resistance of wheat to black point disease caused by Bipolaris sorokiniana, where testing takes places in an indoor, controlled environment. The test method includes surface sterilization of wheat seeds, and cultivating wheat seedlings from the sterilized wheat seeds; preparing conidial suspension of Bipolaris sorokiniana, and spraying the conidial suspension on the seedlings at one-leaf-one-shoot stage; recording the percentage of the diseased leaf area in total leaf area of the first leaf of the wheat seedling on the 10th day of inoculation; calculating the black point incidence of the wheat according to an equation, and then evaluating the resistance of wheat to black point disease caused by Bipolaris sorokiniana through the black point incidence.

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

Abstract: Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

Abstract: A micromachining process to fabricate a single chip that simple drops into a supporting structure. The micromachining process provides the ability to create a probe that will interface with integrated circuits, for example, operating at frequencies in the range of about 100 GHz to about 3,000 GHz (3 THz). This approach creates a silicon structure (or other applicable choice of material) that provides mechanical force for probing while supporting the transfer of the high frequency energy between a measurement system and the integrated circuit, individual device or material.

Abstract: Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace.

Abstract: A micromachining process to fabricate a single chip that simple drops into a supporting structure. The micromachining process provides the ability to create a probe that will interface with integrated circuits, for example, operating at frequencies in the range of about 100 GHz to about 3,000 GHz (3 THz). This approach creates a silicon structure (or other applicable choice of material) that provides mechanical force for probing while supporting the transfer of the high frequency energy between a measurement system and the integrated circuit, individual device or material.