Patents by Inventor Hajime Homma
Hajime Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7408531Abstract: When a discharge start voltage takes a normal value under the normal temperature, priming discharge starts at a time t1. In this case, at a time t3 that is later than the time t1 by a predetermined time t, a sustain driver control signal Ssud2 is raised to put a sustain electrode into the floating state to stop the priming discharge. When the discharge start voltage takes a higher value than usual under the high temperature, the priming discharge starts at a time t2. In this case, at a time t4 that is later than the time t2 by the predetermined time t, the sustain driver control signal Ssud2 is lowered to put the sustain electrode into the floating state to stop the priming discharge. With such a configuration, provided is a plasma display device capable of implementing excellent and stable display quality while maintaining constant, even if a discharge start voltage varies, the charge state in display cells after a priming period, and a drive method for such a plasma display device.Type: GrantFiled: April 13, 2005Date of Patent: August 5, 2008Assignee: Pioneer CorporationInventors: Shinya Tsuchida, Shinji Hirakawa, Mitsuhiro Ishizuka, Koji Hashimoto, Hajime Homma
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Patent number: 7355568Abstract: A length of an addressing period in a first sub-field is made shorter as time from an end of a second sub-field which provides light emission just previously to the first sub-field in a frame including the first and second sub-fields to a start of the first sub-field decreases, and as the number of sustain pulses in the second sub-field increases.Type: GrantFiled: July 24, 2006Date of Patent: April 8, 2008Assignee: Pioneer CorporationInventor: Hajime Homma
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Patent number: 7180482Abstract: A method for driving a plasma display panel in which any one of a scanning electrode and a sustaining electrode is shared by neighboring display cells interposed therebetween. At least one condition selected from the group consisting of a voltage of a sustaining pulse, a pulse width of a sustaining pulse, and a pulse applying interval of a sustaining pulse is changed in relation to a polarity of the sustaining pulse. The sustaining pulse is applied to the scanning electrode and sustaining electrode by a predetermined number with relation to an image data during a sustaining period.Type: GrantFiled: November 23, 2001Date of Patent: February 20, 2007Assignee: Pioneer CorporationInventor: Hajime Homma
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Patent number: 7154189Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.Type: GrantFiled: January 18, 2005Date of Patent: December 26, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
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Publication number: 20060262043Abstract: A length of an addressing period in a first sub-field is made shorter as time from an end of a second sub-field which provides light emission just previously to the first sub-field in a frame including the first and second sub-fields to a start of the first sub-field decreases, and as the number of sustain pulses in the second sub-field increases.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Inventor: Hajime Homma
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Patent number: 7098873Abstract: A length of an addressing period in a first sub-field is made shorter as time from an end of a second sub-field which provides light emission just previously to the first sub-field in a frame including the first and second sub-fields to a start of the first sub-field decreases, and as the number of sustain pulses in the second sub-field increases.Type: GrantFiled: February 27, 2001Date of Patent: August 29, 2006Assignee: Pioneer CorporationInventor: Hajime Homma
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Publication number: 20050264480Abstract: Disclosed is a method of driving a plasma display panel. In this method, one field corresponding to one image is divided into a plurality of sub-fields, and at least one second sub-field is arranged after a first sub-field. In the first sub-field, the method comprises a first step of forming wall charges with negative polarity near the scanning electrode and forming wall charges with positive polarity near the common electrode and the data electrode; a second step of adjusting an amount of the wall charges with negative polarity near the scanning electrode and an amount of the wall charges with positive polarity near the common electrode and the data electrode; a third step of generating a writing discharge in a selected display cell of the display cells; a fourth step of generating light emission for display; and a fifth step of erasing a part of the wall charges in the display cell which emits light in the fourth step.Type: ApplicationFiled: April 13, 2005Publication date: December 1, 2005Inventors: Hajime Homma, Mitsuhiro Ishizuka, Shinji Hirakawa, Shinya Tsuchida, Koji Hashimoto
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Publication number: 20050237276Abstract: When a discharge start voltage takes a normal value under the normal temperature, priming discharge starts at a time t1. In this case, at a time t3 that is later than the time t1 by a predetermined time t, a sustain driver control signal Ssud2 is raised to put a sustain electrode into the floating state to stop the priming discharge. When the discharge start voltage takes a higher value than usual under the high temperature, the priming discharge starts at a time t2. In this case, at a time t4 that is later than the time t2 by the predetermined time t, the sustain driver control signal Ssud2 is lowered to put the sustain electrode into the floating state to stop the priming discharge. With such a configuration, provided is a plasma display device capable of implementing excellent and stable display quality while maintaining constant, even if a discharge start voltage varies, the charge state in display cells after a priming period, and a drive method for such a plasma display device.Type: ApplicationFiled: April 13, 2005Publication date: October 27, 2005Inventors: Shinya Tsuchida, Shinji Hirakawa, Mitsuhiro Ishizuka, Koji Hashimoto, Hajime Homma
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Patent number: 6914584Abstract: When a priming erasure pulse Ppre is applied, weak discharge occurs between a scanning electrode and a sustaining electrode, whereas between the scanning electrode and a data electrode, opposed discharge will not occur or, if any, may occur extremely faintly, and wall charge stuck to the scanning and sustaining electrodes, therefore, is decreased in amount to such an extent that erroneous discharge may not occur in the following address period Ta, so that the data electrode has positive-polarity wall charge left unreduced thereon or has a relatively large amount of wall charge left as stuck thereto, as a result, a sufficient level of write-in discharge can be generated even with a low value of the data voltage Vd.Type: GrantFiled: February 6, 2002Date of Patent: July 5, 2005Assignee: NEC CorporationInventors: Hajime Homma, Yoshito Tanaka, Kota Araki
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Patent number: 6905912Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.Type: GrantFiled: April 7, 2003Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
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Publication number: 20050121761Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.Type: ApplicationFiled: January 18, 2005Publication date: June 9, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
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Patent number: 6828736Abstract: A plasma display panel including a plurality of cells arranged in a matrix, wherein each of the cells includes (a) a scanning electrode having partial cutout, (b) a sustaining electrode having partial cutout, spaced away from the scanning electrode by a discharge gap in mirror-symmetry with a centerline of the discharge gap extending in a first direction, (c) a first trace electrode extending in the first direction on the opposite side of the scanning electrode about the discharge gap such that the first trace electrode makes electrical contact with the scanning electrode and further with a scanning electrode of an adjacent cell, and (d) a second trace electrode extending in the first direction on the opposite side of the sustaining electrode about the discharge gap such that the second trace electrode makes electrical contact with the sustaining electrode and further with a sustaining electrode of an adjacent cell.Type: GrantFiled: January 30, 2003Date of Patent: December 7, 2004Assignee: NEC Plasma Display CorporationInventor: Hajime Homma
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Patent number: 6816136Abstract: A method for driving a PDP is provided which is capable of improving reliability in selective operations, acquiring excellent displaying characteristics, improving contrast, and accommodating a difference in driving characteristics caused by a color to be displayed. If a discharge initiating threshold voltage between surface electrodes is 250 V and the discharge initiating threshold voltage between facing electrodes in a state where lots of activated particles exist in discharging space is 350 V, an ultimate potential of a pre-discharging pulse is set to be 400 V and a electric potential of a pre-discharging pulse is set to be 0 V. When a voltage of the pre-discharging pulse exceeds 250 V being the discharge initiating threshold voltage between surface electrodes, a feeble discharge occurs between surface electrodes.Type: GrantFiled: February 26, 2002Date of Patent: November 9, 2004Assignee: NEC CorporationInventors: Yoshito Tanaka, Hajime Homma, Kota Araki
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Patent number: 6803722Abstract: A plasma display panel is provided with a transparent substrate, and scanning electrodes and sustaining electrodes formed on the transparent substrate extending in a first direction. An area of the scanning electrode is smaller than an area of the sustaining electrode in each of display cells. The widths of the scanning electrode and the sustaining electrode in a second direction crossing the first direction are substantially equal to each other.Type: GrantFiled: November 27, 2001Date of Patent: October 12, 2004Assignee: NEC CorporationInventors: Tadashi Nakamura, Yoshito Tanaka, Hajime Homma, Kouta Araki, Nobumitsu Aibara, Naoto Hirano, Hiroshi Hasegawa
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Patent number: 6795044Abstract: Scanning electrodes are shared between adjacent display lines. Sustaining electrodes are disposed between the scanning electrodes by two. The sustaining electrodes form display lines by gaps with adjacent scanning electrodes. The sustaining electrodes are separated into a first sustaining electrode group in which a plurality of sustaining electrodes disposed at the one side of the scanning electrode are commonly connected and a second sustaining electrode group in which a plurality of sustaining electrodes disposed at the other side of the scanning electrode are commonly connected to be independently driven.Type: GrantFiled: July 2, 2001Date of Patent: September 21, 2004Assignee: NEC CorporationInventors: Yoshito Tanaka, Hajime Homma, Tadashi Nakamura
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Patent number: 6703772Abstract: A plasma display panel has an improved cell electrode structure including: a pair of sustaining and scanning electrodes which are approximately similar or equal in area to each other, and which are different from each other in pattern shape. Each of the scanning electrode alignments further includes a plurality of scanning electrodes. Adjacent two of the scanning electrodes are separated from each other by the separation wall. Each of the sustaining electrode alignments further includes a plurality of sustaining electrodes. Adjacent two of the sustaining electrodes are separated from each other by the separation wall.Type: GrantFiled: March 19, 2002Date of Patent: March 9, 2004Assignee: NEC CorporationInventors: Hiroshi Hasegawa, Nobumitsu Aibara, Naoto Hirano, Tadashi Nakamura, Yoshito Tanaka, Hajime Homma, Kota Araki
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Publication number: 20030207492Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.Type: ApplicationFiled: April 7, 2003Publication date: November 6, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
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Publication number: 20030141824Abstract: A plasma display panel including a plurality of cells arranged in a matrix, wherein each of the cells includes (a) a scanning electrode having partial cutout, (b) a sustaining electrode having partial cutout, spaced away from the scanning electrode by a discharge gap in mirror-symmetry with a centerline of the discharge gap extending in a first direction, (c) a first trace electrode extending in the first direction on the opposite side of the scanning electrode about the discharge gap such that the first trace electrode makes electrical contact with the scanning electrode and further with a scanning electrode of an adjacent cell, and (d) a second trace electrode extending in the first direction on the opposite side of the sustaining electrode about the discharge gap such that the second trace electrode makes electrical contact with the sustaining electrode and further with a sustaining electrode of an adjacent cell.Type: ApplicationFiled: January 30, 2003Publication date: July 31, 2003Applicant: NEC PLASMA DISPLAY CORPORATIONInventor: Hajime Homma
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Patent number: 6582991Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.Type: GrantFiled: June 25, 2001Date of Patent: June 24, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
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Publication number: 20020130618Abstract: A plasma display panel has an improved cell electrode structure including: a pair of sustaining and scanning electrodes which are approximately similar or equal in area to each other, and which are different from each other in pattern shape. Each of the scanning electrode alignments further includes a plurality of scanning electrodes. Adjacent two of the scanning electrodes are separated from each other by the separation wall. Each of the sustaining electrode alignments further includes a plurality of sustaining electrodes. Adjacent two of the sustaining electrodes are separated from each other by the separation wall.Type: ApplicationFiled: March 19, 2002Publication date: September 19, 2002Applicant: NEC CORPORATIONInventors: Hiroshi Hasegawa, Nobumitsu Aibara, Naoto Hirano, Tadashi Nakamura, Yoshito Tanaka, Hajime Homma, Kota Araki