Patents by Inventor Hajime Kamioka
Hajime Kamioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5011783Abstract: A method for producing a semiconductor device including the steps of forming an insulating layer on a substrate, the insulating layer having a plurality of concave portions, forming a non-single crystalline silicon layer on the surface of the insulating layer. The non-single crystalline silicon is patterned so that each concave portion is independently melted and the patterned non-single crystalline silicon layer flows into each of the concave portions to form a single crystalline region by irradiation with an energy ray; and, a semiconductor element is also formed in the single crystalline region.Type: GrantFiled: July 16, 1990Date of Patent: April 30, 1991Assignee: Fujitsu LimitedInventors: Tsutomu Ogawa, Hajime Kamioka, Seiichiro Kawamura, Junji Sakurai
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Patent number: 4672740Abstract: A semiconductor device having contact windows between an aluminum or aluminum-alloy wiring layer and a diffused region in a semiconductor substrate, in which the contacts are formed by using a barrier film on a refractory metal silicide between the wiring layer and the diffused region. The barrier film comprising the refactory metal and silicon is beam annealed for a short period of time such as, 10 seconds or less, so that adverse effects of the barrier film can be prevented while an excellent electrical or ohmic contact between the wiring layer and the diffused layer can be obtained.Type: GrantFiled: August 28, 1984Date of Patent: June 16, 1987Assignee: Fujitsu LimitedInventors: Kazunari Shirai, Hajime Kamioka, Shigeyoshi Koike
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Patent number: 4642883Abstract: Disclosed is a structure of a semiconductor integrated circuit device including circuit elements such as a bipolar transistor and I.sup.2 L. The structure comprises a buried layer formed by the ion implantation method using an insulating layer, having a window with tapered edges at the surface of semiconductor substrate, as a mask. A part of the buried layer appears at the surface of the semiconductor substrate, thus establishing the connection of electrodes. The circuit element is formed in the region bounded by the buried layer and the window.Type: GrantFiled: January 28, 1985Date of Patent: February 17, 1987Assignee: Fujitsu LimitedInventors: Junji Sakurai, Hajime Kamioka
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Patent number: 4503315Abstract: A semiconductor device with a fuse including an insulating layer having at least one step. A fusible film on the insulating layer crosses the step and a covering film is formed on the fusible film, the step and the insulating layer. When the portion of the fusible film crossing the step is irradiated with a laser beam the portion of the fusible film on the upper surface of the insulating layer melts and flows onto the lower surface of the insulating layer without forming a hole, thereby separating the fusible film at the step.Type: GrantFiled: December 27, 1982Date of Patent: March 5, 1985Assignee: Fujitsu LimitedInventors: Hajime Kamioka, Mikio Takagi, Noriaki Sato, Motoo Nakano, Takashi Iwai
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Patent number: 4412388Abstract: A method for drying semiconductor substrates wherein a plurality of semiconductor substrates are irradiated with electromagnetic waves emitted from a waveguide in a non-reactive atmosphere of normal atmospheric pressure while the semiconductor substrates are positioned so that the predominant faces thereof substantially form right angles to the face of an opening of the waveguide.Type: GrantFiled: December 22, 1980Date of Patent: November 1, 1983Assignee: Fujitsu LimitedInventors: Mikio Takagi, Hajime Kamioka
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Patent number: 4375993Abstract: A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then annealing the semiconductor layer by means of a first laser with a second laser being applied to the insulator layer to heat it while the first layer is applied to the semiconductor laser.Type: GrantFiled: April 8, 1981Date of Patent: March 8, 1983Assignee: Fujitsu LimitedInventors: Haruhisa Mori, Hajime Kamioka, Motoo Nakano, Nobuo Sasaki
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Patent number: 4333774Abstract: A base region of a walled emitter type bipolar transistor is formed by an ion implantation process. During the ion implantation, insulating films are disposed on a part of a semiconductor body corresponding to an emitter region, so that the obtained profile of a base-collector junction is terraced, namely, a part of the base-collector junction which is below the insulating films is shallower than the rest of the base-collector junction.Type: GrantFiled: March 14, 1980Date of Patent: June 8, 1982Assignee: Fujitsu LimitedInventor: Hajime Kamioka
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Patent number: 4293589Abstract: A process for high pressure oxidation of silicon comprising the steps of inserting silicon wafers and an oxidizing substance into a quartz capsule sealing the quartz capsule gas-tightly by fusing, and heating the quartz capsule to generate a high pressure oxidizing atmosphere therein and to form an oxide film on the silicon wafers without a flow of the oxidizing atmosphere. In a case where water is used as the oxidizing substance, the water is frozen and the inside space of the quartz capsule is exhausted before the sealing operation. Furthermore, in a case where an oxidizing gas, e.g. oxygen gas, is used as the oxidizing substance, if the pressure of the gas is higher than the ambient pressure, the quartz capsule is cooled to decrease the gas pressure to a pressure below the ambient pressure before the sealing operation.Type: GrantFiled: October 1, 1980Date of Patent: October 6, 1981Assignee: Fujitsu LimitedInventors: Mikio Takagi, Mamoru Maeda, Hajime Kamioka
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Patent number: 4293590Abstract: A process for high pressure oxidation of silicon comprising the steps of inserting silicon wafers and an oxidizing substance into a quartz capsule sealing the quartz capsule gas-tightly by fusing, and heating the quartz capsule to generate a high pressure oxidizing atmosphere therein and to form an oxide film on the silicon wafers without a flow of the oxidizing atmosphere. In a case where water is used as the oxidizing substance, the water is frozen and the inside space of the quartz capsule is exhausted before the sealing operation. Furthermore, in a case where an oxidizing gas, e.g. oxygen gas, is used as the oxidizing substance, if the pressure of the gas is higher than the ambient pressure, the quartz capsule is cooled to decrease the gas pressure to a pressure below the ambient pressure before the sealing operation.Type: GrantFiled: October 1, 1980Date of Patent: October 6, 1981Assignee: Fujitsu LimitedInventors: Mikio Takagi, Mamoru Maeda, Hajime Kamioka
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Patent number: 4275094Abstract: A process for high pressure oxidation of silicon comprising the steps of inserting silicon wafers and an oxidizing substance into a quartz capsule sealing the quartz capsule gas-tightly by fusing, and heating the quartz capsule to generate a high pressure oxidizing atmosphere therein and to form an oxide film on the silicon wafers without a flow of the oxidizing atmosphere. In a case where water is used as the oxidizing substance, the water is frozen and the inside space of the quartz capsule is exhausted before the sealing operation. Furthermore, in a case where an oxidizing gas, e.g. oxygen gas, is used as the oxidizing substance, if the pressure of the gas is higher than the ambient pressure, the quartz capsule is cooled to decrease the gas pressure to a pressure below the ambient pressure before the sealing operation.Type: GrantFiled: October 30, 1978Date of Patent: June 23, 1981Assignee: Fujitsu LimitedInventors: Mikio Takagi, Mamoru Maeda, Hajime Kamioka
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Patent number: 4210473Abstract: Disclosed is a process for producing a semiconductor device, especially, a high speed silicon gate field effect semiconductor device, by diffusing an impurity substance, such as arsenic or phosphorus, into a polycrystalline silicon layer to be converted into a silicon gate having a high electroconductivity and into portions of a single crystal silicon substrate to be converted into source and drain regions, in a sealed capsule, at an elevated temperature, under a vacuum. During the above-mentioned diffusing operation, the impurity substance can diffuse into the polycrystalline silicon layer at a higher diffusing speed than into the single crystal silicon substrate.Type: GrantFiled: October 30, 1978Date of Patent: July 1, 1980Assignee: Fujitsu LimitedInventors: Mikio Takagi, Hajime Kamioka, Haruo Shimoda, Hidekazu Miyamoto
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Patent number: 3940288Abstract: A method of making a semiconductor device capable of high-speed operation is disclosed in which when the current gain-bandwidth is increased by the formation of a shallow base region. A side etching process is used to decrease the base spreading resistance and to allow ease in the formation of an emitter region of fine pattern. When the emitter region is formed by using polycrystalline silicon as a source of impurity diffusion, that area of an insulating film on a semiconductor substrate which adjoins the polycrystalline silicon is removed before the impurity diffusion so as to prevent an abnormal diffusion phenomenon.Type: GrantFiled: May 10, 1974Date of Patent: February 24, 1976Assignee: Fujitsu LimitedInventors: Mikio Takagi, Hajime Kamioka, Kazufumi Nakayama, Haruo Shimoda