Patents by Inventor Hajime Kaneko
Hajime Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830232Abstract: An image judgment apparatus stores, in a memory, a judgment model configured to learn about each of the plurality of judgment items based on first data corresponding to an image as a reference with which to judge good and second data corresponding to an image as a reference with which to judge not good, sets a plurality of magnifications for each of the plurality of judgment items, segments part of the image, generates image data at the plurality of magnifications from the segmented image, inputs the generated image data corresponding to each of the plurality of magnifications to the judgment model, and judges, based on output results from the judgment model, whether the quality of the image is good or not good with respect to each of the plurality of judgment items.Type: GrantFiled: September 16, 2020Date of Patent: November 28, 2023Assignee: Canon Kabushiki KaishaInventors: Satoshi Shimazu, Hajime Kaneko
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Publication number: 20210099610Abstract: An image judgment apparatus stores, in a memory, a judgment model configured to learn about each of the plurality of judgment items based on first data corresponding to an image as a reference with which to judge good and second data corresponding to an image as a reference with which to judge not good, sets a plurality of magnifications for each of the plurality of judgment items, segments part of the image, generates image data at the plurality of magnifications from the segmented image, inputs the generated image data corresponding to each of the plurality of magnifications to the judgment model, and judges, based on output results from the judgment model, whether the quality of the image is good or not good with respect to each of the plurality of judgment items.Type: ApplicationFiled: September 16, 2020Publication date: April 1, 2021Inventors: Satoshi Shimazu, Hajime Kaneko
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Patent number: 10797077Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: December 3, 2019Date of Patent: October 6, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Publication number: 20200111809Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: December 3, 2019Publication date: April 9, 2020Applicant: Toshiba Memory CorporationInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
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Patent number: 10541251Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: July 23, 2018Date of Patent: January 21, 2020Assignee: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Patent number: 10535678Abstract: A semiconductor memory device includes a first member spreading along a first direction and a second direction, a stacked body provided on a third-direction side when viewed from the first member, and a second member provided inside the first member and exposed at a surface of the first member on the third-direction side. A configuration of an end portion in the first direction of the stacked body is a staircase configuration having terraces formed every conductive film. The second member is made from a material different from a material of the first member. The second member is totally disposed in a region opposing a total length of an end edge of the stacked body on the first-direction side, and not disposed in an outer region of the stacked body on the second-direction side.Type: GrantFiled: September 12, 2018Date of Patent: January 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hajime Kaneko, Takuya Inatsuka, Hideki Inokuma
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Publication number: 20190393236Abstract: A semiconductor memory device includes a first member spreading along a first direction and a second direction, a stacked body provided on a third-direction side when viewed from the first member, and a second member provided inside the first member and exposed at a surface of the first member on the third-direction side. A configuration of an end portion in the first direction of the stacked body is a staircase configuration having terraces formed every conductive film. The second member is made from a material different from a material of the first member. The second member is totally disposed in a region opposing a total length of an end edge of the stacked body on the first-direction side, and not disposed in an outer region of the stacked body on the second-direction side.Type: ApplicationFiled: September 12, 2018Publication date: December 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hajime Kaneko, Takuya Inatsuka, Hideki Inokuma
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Publication number: 20180350834Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N-2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: July 23, 2018Publication date: December 6, 2018Applicant: Toshiba Memory CorporationInventors: Genki Kawaguchi, Masanari Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Patent number: 10074665Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: September 6, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Genki Kawaguchi, Masanori Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Publication number: 20170077108Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: September 6, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
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Patent number: 9548310Abstract: According to an embodiment, a semiconductor device includes a semiconductor substrate, a first region that is provided on the semiconductor substrate and has a line-and-space pattern extending in a first direction, and a second region that is provided adjacent to the first region on the semiconductor substrate and has a dummy pattern. The surface area per unit area of the second region is greater than the surface area per unit area of the first region.Type: GrantFiled: February 2, 2015Date of Patent: January 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Kaneko, Satoshi Nagashima
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Publication number: 20160040744Abstract: Provided is a damping material capable of exhibiting a damping effect more effective than that of a conventional technique. A composite damping material of the present invention is a material in which a needle-like dielectric having a high dielectric constant made of a titanium dioxide and a piezoelectric fiber made of an organic material are mixed in a polymer material serving as a matrix, and preferably a material in which a flat filler made of an inorganic material and conductive fine particles are further mixed. A material made of a cellulose fiber can be used preferably as the piezoelectric fiber.Type: ApplicationFiled: September 28, 2015Publication date: February 11, 2016Inventors: Masao SUMITA, Hajime KANEKO, Kazutaka MURASE
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Publication number: 20160005752Abstract: According to an embodiment, a semiconductor device includes a semiconductor substrate, a first region that is provided on the semiconductor substrate and has a line-and-space pattern extending in a first direction, and a second region that is provided adjacent to the first region on the semiconductor substrate and has a dummy pattern. The surface area per unit area of the second region is greater than the surface area per unit area of the first region.Type: ApplicationFiled: February 2, 2015Publication date: January 7, 2016Inventors: Hajime KANEKO, Satoshi NAGASHIMA
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Patent number: 9196609Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.Type: GrantFiled: March 13, 2014Date of Patent: November 24, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hajime Kaneko, Keiichi Shimada, Takamasa Usui
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Publication number: 20150076708Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.Type: ApplicationFiled: March 13, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hajime KANEKO, Keiichi Shimada, Takamasa Usui
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Publication number: 20150061153Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first region and a second region, a first insulating layer provided above the semiconductor layer, an extending first contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a first element provided in the first region, an extending second contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a second element provided in the second region, an extending first interconnection layer connected to an upper end of the first contact electrode, and having a sidewall surrounded with the first insulating layer, and an extending second interconnection layer connected to an upper end of the second contact electrode, having a sidewall surrounded with the first insulating layer, and having a line width wider than a line width of the first interconnection layer.Type: ApplicationFiled: March 11, 2014Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki HIMENO, Yuki SOH, Hajime KANEKO
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Patent number: 8540335Abstract: A printing apparatus capable of specifying the color material concentration in ink can discharge or suck the ink in a suitable amount for suppressing degradation in print quality or ink supply failure. The printing apparatus executes printing by scanning a printhead having an orifice to discharge ink. The printing apparatus includes a scanning unit which scans the printhead without discharging the ink to generate a discharge failure orifice, and a detection unit which detects the presence of the discharge failure orifice. The color material concentration in the ink is estimated on the basis of the number of times or the time of scanning without discharging the ink required until the detection unit detects the presence of the discharge failure orifice.Type: GrantFiled: November 16, 2007Date of Patent: September 24, 2013Assignee: Canon Kabushiki KaishaInventors: Yasushi Nakano, Hajime Kaneko
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Patent number: 7523160Abstract: An information provision exchange service system that can securely prevent the transmission of information that can be used to identify a user to another party and enable users to provide and exchange information between themselves free from confidentiality concerns. A server checks registered personal information to determine whether or not information that can be used to identify any of the users using a plurality of communication terminals is included in information exchanged between the communication terminals via a communication network, and replaces the information that can be used to identify a user with other information if the information that can be used to identify the user is detected in the information exchanged between the communication terminals via the communication network.Type: GrantFiled: February 12, 2004Date of Patent: April 21, 2009Assignee: Canon Kabushiki KaishaInventors: Masataka Eida, Hajime Kaneko
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Patent number: 7396110Abstract: An ink container capable of being simply mounted in a holder with a small working space includes a rib-like guide portion for determining a mounting path during mounting of the ink container in a head cartridge at a side surface. The head cartridge includes a holder portion provided with a sliding projection which slides in contact with the guide portion. When the ink container is mounted, a user moves the ink container so that a first inclined portion first contacts the sliding projection and thereafter the ink contained is moved in an obliquely below direction toward the head cartridge while sliding the sliding projection along the first inclined portion.Type: GrantFiled: September 26, 2005Date of Patent: July 8, 2008Assignee: Canon Kabushiki KaishaInventors: Nobuyuki Matsumoto, Hajime Kaneko
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Publication number: 20080122891Abstract: This invention is directed to a printing apparatus capable of specifying the color material concentration in ink to discharge or suck the ink in a suitable amount for suppressing degradation in print quality or ink supply failure. The printing apparatus executes printing by scanning a printhead having an orifice to discharge ink. The printing apparatus includes a scanning unit which scans the printhead without discharging the ink to generate a discharge failure orifice, and a detection unit which detects the presence of the discharge failure orifice. The color material concentration in the ink is estimated on the basis of the number of times or the time of scanning without discharging the ink required until the detection unit detects the presence of the discharge failure orifice.Type: ApplicationFiled: November 16, 2007Publication date: May 29, 2008Applicant: CANON KABUSHIKI KAISHAInventors: Yasushi Nakano, Hajime Kaneko