Patents by Inventor Hajime Kimura

Hajime Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450291
    Abstract: The resolution of a low-resolution image is made high and a stereoscopic image is displayed. Resolution is made high by super-resolution processing. In this case, the super-resolution processing is performed after edge enhancement processing is performed. Accordingly, a stereoscopic image with high resolution and high quality can be displayed. Alternatively, after image analysis processing is performed, edge enhancement processing and super-resolution processing are concurrently performed. Accordingly, processing time can be shortened.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: September 20, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hajime Kimura
  • Publication number: 20220293603
    Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 15, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Tatsuya ONUKI, Hajime KIMURA, Takayuki IKEDA, Shunpei YAMAZAKI
  • Publication number: 20220293159
    Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Hajime KIMURA, Atsushi MIYAGUCHI, Tatsunori INOUE
  • Patent number: 11444106
    Abstract: In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: September 13, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11442317
    Abstract: The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 13, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Publication number: 20220283661
    Abstract: An input/output device includes a first sensor electrode and a second sensor electrode. In addition, the input/output device includes a first electrode and a second electrode which are electrodes for a display element, and a substrate sandwiched between the first sensor electrode and the second sensor electrode. The second sensor electrode is formed concurrently with the first electrode using the same material. The input/output device sensors a change in capacitance of a capacitor formed between the first sensor electrode and the second sensor electrode. Furthermore, a third sensor electrode to which a floating potential is applied may be provided to overlap with the first electrode. In the input/output device, either a liquid crystal element or a light-emitting element may be used, or both the liquid crystal element and the light-emitting element may be used.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Hajime KIMURA, Shunpei YAMAZAKI
  • Patent number: 11435626
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 6, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11430899
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
  • Publication number: 20220269118
    Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a first pixel, a second pixel, and a functional layer. The first pixel includes a first display element, and the second pixel includes a second display element. The functional layer includes a first pixel circuit and a second pixel circuit. The first display element includes a first electrode, a second electrode, and a layer containing a liquid crystal material. A first distance is provided between the first electrode and the functional layer. A second distance is provided between the second electrode and the functional layer. The first electrode and the second electrode each include a region overlapping with the layer containing a liquid crystal material. The second distance is shorter than the first distance. The second display element includes a third electrode, a fourth electrode, and the layer containing a liquid crystal material.
    Type: Application
    Filed: May 16, 2022
    Publication date: August 25, 2022
    Inventor: Hajime KIMURA
  • Patent number: 11422423
    Abstract: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 23, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toru Takayama, Satoshi Murakami, Hajime Kimura
  • Patent number: 11424737
    Abstract: In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshiyuki Kurokawa, Tatsunori Inoue
  • Publication number: 20220262438
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 22, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO
  • Publication number: 20220262858
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 31, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO, Hiromichi GODO, Kazuki TSUDA, Hitoshi KUNITAKE
  • Publication number: 20220262822
    Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Hajime KIMURA, Tatsunori INOUE
  • Patent number: 11417720
    Abstract: A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held. Accordingly, variation in current value caused by variation in threshold voltage of the transistor can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In addition, a display device with a high duty ratio can be provided by changing a potential of the power supply line.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 16, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11417704
    Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 16, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshiyuki Kurokawa
  • Publication number: 20220255511
    Abstract: A communication device that can transmit and receive a signal with a large amplitude is provided. The communication device includes an amplifier circuit including first to fourth transistors, first to fourth bias transistors, first to fourth loads, and first to fourth terminals. The drains of the first to fourth transistors are electrically connected to the sources of the first to fourth bias transistors. The sources of the first to fourth transistors are electrically connected to power supply lines. The gates of the first and second bias transistors are electrically connected to a first wiring, and the gates of the third and fourth bias transistors are electrically connected to a second wiring. The first to fourth terminals are electrically connected to the gates of the first to fourth transistors, the drains of the third, fourth, first, and second bias transistors, and the first to fourth loads.
    Type: Application
    Filed: May 19, 2020
    Publication date: August 11, 2022
    Inventors: Hajime KIMURA, Takayuki IKEDA
  • Publication number: 20220237440
    Abstract: A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits.
    Type: Application
    Filed: May 7, 2020
    Publication date: July 28, 2022
    Inventors: Hajime KIMURA, Munehiro KOZUMA
  • Publication number: 20220238563
    Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.
    Type: Application
    Filed: January 28, 2022
    Publication date: July 28, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Publication number: 20220229336
    Abstract: To improve viewing angle characteristics by varying voltage which is applied between liquid crystal elements. A liquid crystal display device in which one pixel is provided with three or more liquid crystal elements and the level of voltage which is applied is varied between the liquid crystal elements is varied. In order to vary the level of the voltage which is applied between the liquid crystal elements, an element which divides the applied voltage is provided. In order to vary the level of the applied voltage, a capacitor, a resistor, a transistor, or the like is used. Viewing angle characteristics can be improved by varying the level of the voltage which is applied between the liquid crystal elements.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventor: Hajime Kimura