Abstract: A microprocessor which can simultaneously execute a plurality of instructions (predetermined number of instructions, i.e., m-instructions which are transferred to a plurality of registers. When the instructions within the m-instructions are transferred to the registers, the instructions are executed in order of the executable state of the instructions regardless of order of the transfer. Further, when n-instructions (n>m) are simultaneously set to the executable state for every one clock cycle, the n-instructions are executed in order of the transfer of the instructions. Accordingly, it is possible to realize high speed and effective execution of instructions.

Abstract: A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circuits each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means and a real carry signal generating means. The carry select adder circuit does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on a carry propagate signal, a cumulative carry propagate signal and a cumulative carry generate signal which are necessary for generating the presumed sum signal pair and a real carry signal to calculate the real sum signal.

Abstract: An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.

Abstract: A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

Abstract: A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprises a plurality of input/output cells being arranged in a peripheral region on a semiconductor chip; a plurality of basic cell columns each comprising a plurality of basic cells arranged in a predetermined direction, each basic cell constituting transistors; an interconnection region formed on the chip, for accommodating a data bus; and a plurality of latch cells being arranged in the basic cell columns, for keeping a potential of a data bus laid on the interconnection region to prevent the data bus from being changed into a floating state, each latch cell comprising transistors, each of which has a driving capability smaller than that of each transistor of the basic cell.