Patents by Inventor Hajime Kuriyama

Hajime Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6988233
    Abstract: A decoding apparatus and decoding method for performing iteration decoding the suitable number of iterations, and thereby securing the desired transmission quality while decreasing the processing delay. Turbo decoder 301 iterates error correcting decoding on input coded sequences. Error checker 302 decodes an error detecting code contained in a decoded result of the error correcting decoding, and checks whether or not an error remains in the decoded result in turbo decoder 301. Iteration controller 303 instructs turbo decoder 301 to continue the iteration decoding until the number of iterations in the iteration decoding is more than or equal to the constraint number of iterations and error checker 302 determines no error in the decoded result.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: January 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirokazu Kanai, Hajime Kuriyama
  • Publication number: 20030023909
    Abstract: Memory address generation apparatus 12 generates memory addresses, multiplier 15 reads from memory 14 storing row transposition patterns of a matrix a row transposition pattern value corresponding to the row number outputfrom row counter 11 and calculates an address offset value by multiplying the transposition pattern value of the read row by the number of columns of the matrix, adder 16 reads from memory 13 storing row transposition patterns of the matrix a column transposition pattern value corresponding to the memory address generated by the memory address generation apparatus and generates an interleave address by adding up the transposition pattern value of the read column and the address offset value.
    Type: Application
    Filed: November 7, 2001
    Publication date: January 30, 2003
    Inventors: Tetsuya Ikeda, Hidetoshi Suzuki, Ryutaro Yamanaka, Hajime Kuriyama
  • Publication number: 20030009719
    Abstract: A decoding apparatus and decoding method for performing iteration decoding the suitable number of iterations, and thereby securing the desired transmission quality while decreasing the processing delay. Turbo decoder 301 iterates error correcting decoding on input coded sequences. Error checker 302 decodes an error detecting code contained in a decoded result of the error correcting decoding, and checks whether or not an error remains in the decoded result in turbo decoder 301. Iteration controller 303 instructs turbo decoder 301 to continue the iteration decoding until the number of iterations in the iteration decoding is more than or equal to the constraint number of iterations and error checker 302 determines no error in the decoded result.
    Type: Application
    Filed: July 23, 2002
    Publication date: January 9, 2003
    Inventors: Hirokazu Kanai, Hajime Kuriyama