Patents by Inventor Hajime MASUBUCHI

Hajime MASUBUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 10128345
    Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Yoshitaka Nishimura, Akio Kitamura, Hajime Masubuchi, Souichi Yoshida
  • SEMICONDUCTOR DEVICE
    Publication number: 20180166549
    Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
    Type: Application
    Filed: October 25, 2017
    Publication date: June 14, 2018
    Inventors: Ryoichi KATO, Hiromichi GOHARA, Takafumi YAMADA, Kohei YAMAUCHI, Tatsuhiko ASAI, Yoshitaka NISHIMURA, Akio KITAMURA, Hajime MASUBUCHI, Souichi YOSHIDA