Abstract: An exemplary embodiment of the present invention aims at providing a cooling structure for a test device which has sufficient cooling performance and can reduce the size of the heat sink. The cooling structure for a test device has first and second plates, a cover with a hole on the first plate, and a heat sink attached to the cover. When the vacuum suction is applied in a test space which is formed between the first and the second plates, air is drawn through the hole of the cover and applied onto the heat sink.

Abstract: An evaluation LSI includes a noise generation circuit generating a controlled amount of noise controlled from outside of the LSI, and a delay measurement circuit measuring a signal delay of a delay circuit influenced by the noise. The relationship between the amount of noise and the signal delay is determined. A device-under-test (DUT) LSI includes a functional circuit and a delay circuit having a signal delay influenced by the operation of the functional test. By evaluating the signal delay of the delay circuit in the DUT LSI, the amount of noise therein is estimated based on the determined relationship.

Abstract: A semiconductor device socket, in which a semiconductor device is installed, includes a support member on which a substrate is placed, an anisotropic conductive sheet that acts as an intermediary in electric connection between the substrate and the semiconductor device, and heater which heats the anisotropic conductive sheet. The heater heats the anisotropic conductive sheet for expanding the sheet before the semiconductor device is installed in the semiconductor device socket. The semiconductor device is installed in the socket after the anisotropic conductive sheet has been expanded by heat from the heater.

Abstract: An evaluation LSI includes a noise generation circuit generating a controlled amount of noise controlled from outside of the LSI, and a delay measurement circuit measuring a signal delay of a delay circuit influenced by the noise. The relationship between the amount of noise and the signal delay is determined. A device-under-test (DUT) LSI includes a functional circuit and a delay circuit having a signal delay influenced by the operation of the functional test. By evaluating the signal delay of the delay circuit in the DUT LSI, the amount of noise therein is estimated based on the determined relationship.

Abstract: A semiconductor device socket, in which a semiconductor device is installed, includes a support member on which a substrate is placed, an anisotropic conductive sheet that acts as an intermediary in electric connection between the substrate and the semiconductor device, and heater which heats the anisotropic conductive sheet. The heater heats the anisotropic conductive sheet for expanding the sheet before the semiconductor device is installed in the semiconductor device socket. The semiconductor device is installed in the socket after the anisotropic conductive sheet has been expanded by heat from the heater.

Abstract: A semiconductor device socket, in which a semiconductor device is installed, includes a support member on which a substrate is placed, an anisotropic conductive sheet that acts as an intermediary in electric connection between the substrate and the semiconductor device, and heater which heats the anisotropic conductive sheet. The heater heats the anisotropic conductive sheet for expanding the sheet before the semiconductor device is installed in the semiconductor device socket. The semiconductor device is installed in the socket after the anisotropic conductive sheet has been expanded by heat from the heater.

Abstract: An electronic device test system includes electronic equipment having a board on which pluralities of electronic devices are mounted and isolation means which isolates from surrounding air an electronic device to be tested. When executing an electronic device test, the electronic device to be tested, which is one of the plurality of electronic devices mounted on the board of the electronic equipment, is isolated from surrounding air by the isolation means. After that, a power supply voltage is applied to the electronic equipment and an electric signal is applied to the electronic device for testing the electronic device.

Abstract: A semiconductor device socket, in which a semiconductor device is installed, includes a support member on which a substrate is placed, an anisotropic conductive sheet that acts as an intermediary in electric connection between the substrate and the semiconductor device, and heater which heats the anisotropic conductive sheet. The heater heats the anisotropic conductive sheet for expanding the sheet before the semiconductor device is installed in the semiconductor device socket. The semiconductor device is installed in the socket after the anisotropic conductive sheet has been expanded by heat from the heater.

Abstract: An electronic device test system includes electronic equipment having a board on which pluralities of electronic devices are mounted and isolation means which isolates from surrounding air an electronic device to be tested. When executing an electronic device test, the electronic device to be tested, which is one of the plurality of electronic devices mounted on the board of the electronic equipment, is isolated from surrounding air by the isolation means. After that, a power supply voltage is applied to the electronic equipment and an electric signal is applied to the electronic device for testing the electronic device.

Abstract: A circuit board test fixture includes probe pins that contact connection terminals of the board. The probe pins are electrically connected without applying a force directly to the board by placing the probe pins in sleeves and by sliding the probe pins into contact with connection terminals with air pressure.

Abstract: In an electronic device structure, a high dam is formed on a circuit board so as to enclose input/output terminals of an electronic component mounted on the circuit board. The input/output terminals are projected from a body of the electronic component and connected to a printed circuit formed on the circuit board. The body is covered with a metal case.

Abstract: In a large-scale integrated circuit, a scan path is divided between an I/O scan path that is formed by a series connection between only flip-flops that are in a region near an I/O pin and an internal scan path that is formed by a series connection between other flip-flops. A selector has one of its inputs connected to another end of the I/O scan path and to one end of the internal scan path, another of its inputs connected to another end of the internal scan path, and its output connected to a scan out. This selector, based on a test mode signal, selects either all scan paths or only the I/O scan path.

Abstract: A plurality of indentations 21, 22, and 23 are formed in one major surface of a printed board 1. A plurality of electrode pads 41, 42, 43, and 44 are provided on the one major surface and the bottom of the indentations. A plurality of solder portions 91, 92, 93, and 94 are formed on the respective electrode pads. A plurality of electronic components 5, 6, 7, and 8 each having a plurality of terminals are connected to the electrode pads in the corresponding indentations by means of the solder portions.

Abstract: A scan path circuit is for use in testing a logic package designed in accordance with scan path fashion. The logic package comprises a logic circuit and a plurality of scan paths. The logic circuit has first through N-th input/output pins, where N represents a positive integer which is greater than one. The scan paths are connected in serial to one another and are connected to the logic circuit. The scan path circuit comprises first through N-th memory sections which are connected in serial to one another and which are connected to the first through the N-th input/output pins, respectively. Each of the memory sections comprises a first memory circuit and a second memory circuit. The first memory circuit of an n-th memory section supplies test input to an n-th input/output pin in a shifting mode, where n is a variable between one and N. The first memory circuit of the n-th memory section takes test output from the logic circuit through the n-th input/output pin in a normal mode.