Abstract: A substrate processing method includes: (A) preparing a substrate, on which a high-dielectric film having a higher permittivity than a SiO2 film is formed; (B) supplying, to the substrate, a metal solution containing a second metal element having a higher electronegativity or a lower valence than a first metal element contained in the high-dielectric film; and (C) forming a doping layer, in which the first metal element is substituted with the second metal element, on a surface of the high-dielectric film.

Abstract: A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Abstract: This film formation method comprises: a first film formation step; a second film formation step; and a third film formation step. In the first film formation step, a dielectric film is formed on a first conductive film. In the second film formation step, a metal oxide film is formed on the dielectric film. In addition, in the second film formation step, a metal oxide film is formed using heated oxygen gas and a vapor of an organic metal compound. In the third film formation step, a second conductive film is formed on the metal oxide film.

Abstract: A pattern formation method includes: forming a photosensitive hard mask made of a transition metal oxide film on a surface of a substrate; exposing the photosensitive hard mask to EUV light in a desired pattern; causing a state change in an exposed region by heat generated during exposure; and selectively removing either a region where the state change has occurred or a region where the state change has not occurred.

Abstract: There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

Abstract: A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Abstract: A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO2, Pt, Pd, CuO, and CuO2, using an Ru(EtCp)2 gas and an O2 gas; and selectively forming a first SiO2-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

Abstract: There is provided a semiconductor device. The semiconductor device includes a first electrode made of a metal, a first semiconductor, a first insulating film configured to be provided between the first electrode and the first semiconductor and to be made of an insulating transition metal oxide and an intermediate film configured to be provided between the first electrode and the first insulating film. A lower end of a conduction band of the intermediate film is lower than a Fermi level of the metal constituting the first electrode.

Abstract: A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO2, Pt, Pd, CuO, and CuO2, using an Ru(EtCp)2 gas and an O2 gas; and selectively forming a first SiO2-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiO2 film only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

Abstract: There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Abstract: A switch device used in a crossbar memory array having a non-volatile memory includes: a laminated body formed of a semiconductor film and an insulating film laminated on the semiconductor film; and a pair of electrode layers having the laminated body therebetween. The semiconductor film is made of a semiconductor material having an I-V characteristic with a negative resistance region.

Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Abstract: The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.

Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r1 of the sacrificial oxide film is higher than an etching rate r2 of the buried oxide layer during the etching.

Abstract: The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.

Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r1 of the sacrificial oxide film is higher than an etching rate r2 of the buried oxide layer during the etching.