Abstract: A method of simulating a PLL circuit is provided, which makes it possible to accurately judge the frequency of the feedback clock signal to conduct simulation even if the frequency of the output clock signal is changed according to the necessity. The PLL circuit has a reference input terminal into which a reference clock signal with a reference clock frequency is inputted, a feedback input terminal into which a feedback clock signal is inputted, and output terminals from which output clock signals are outputted. The output clock signals include at least one of a multiplied output clock signal and a divided output clock signal. In the step (a), different dummy signals are outputted to the output terminals, respectively. In the step (b), a signal fed back to the feedback input terminal is detected to find which one of the dummy signals the signal thus fed back corresponds to, thereby recognizing which one of the output terminals is connected to the feedback input terminal.

Abstract: In a logical synthesize design for an ASIC using a general purpose macro, to execute automatically retrieval/elimination of a redundancy function at a function level and to optimize the circuit precisely and speedily, a redundancy conditional statement retrieval unit 3 comprises a conditional statement retrieval unit 31 for retrieving a conditional statement to indicate a condition of an output versus an input from an input macro logical descriptive data; a state transition display descriptive addition unit 32 for producing an intermediate logical descriptive data to which a state transition data is added based on the retrieved conditional statement; a logical simulation unit 34 for executing a logical simulation of an operation mode control data and an input macro logical descriptive data to output status value data; an invariable conditional statement discrimination unit 36 for discriminating and extracting an invariable conditional statement having an invariable status value, based on the status value data