Abstract: A semiconductor device is configured to increase energy absorbed by an active clamp. The semiconductor device comprises a semiconductor element, a sealing resin, and a coating member. The semiconductor element includes a first electrode. The sealing resin covers the semiconductor element. The coating member is interposed between the first electrode and the sealing resin. The coating member contains a material with higher thermal conductivity than the sealing resin.

Abstract: A semiconductor device includes: a semiconductor region of a first conductivity type having a main surface; a capacitor region of a second conductivity type formed in a surface layer portion of the main surface; and at least one trench structure including a trench formed in the main surface to penetrate the capacitor region, an insulating film covering a wall surface of the trench, and embedded electrodes embedded in the trench so as to form capacitive coupling with the capacitor region through the insulating film.

Abstract: A semiconductor device includes: an n-type semiconductor layer; a p-type drift region formed in a surface layer of the n-type semiconductor layer; an n-type body region formed in the surface layer of the n-type semiconductor layer so as to be spaced apart from or adjacent to the p-type drift region; a p-type drain region formed in a surface layer of the p-type drift region; a p-type source region formed in a surface layer of the n-type body region; a gate insulating film formed over a surface of the n-type semiconductor layer so as to straddle the p-type drift region and the n-type body region; a gate electrode formed over the gate insulating film; and an n-type region formed in the surface layer of the p-type drift region and arranged between a side edge of the p-type drift region near the n-type body region and the p-type drain region.

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

Abstract: This fuel tank dam closes a gap between a first structural component fixed to the inside surface of the outer plate of a fuel tank and a second structural component provided with a cutout part into which the first structural component is inserted. This fuel tank dam includes: a first portion that can be fixed to the first structural component; a second portion that has a surface extending in a direction intersecting with the first portion and can be fixed to the second structural component; and a third portion that has a bellows and is disposed between the first portion and the second portion. This fuel tank dam is configured such that the first portion, the second portion, and the third portion are integrated, the bellows has a thickness of 0.381 to 1.524 mm, and the second portion has a thickness of 0.762 to 7.620 mm.

Abstract: A semiconductor device includes a semiconductor chip which has a main surface and a main transistor which includes a first system transistor and a second system transistor that are each formed in the main surface so as to be individually controlled, in which the first system transistor includes a first composite cell which is constituted of an ?-number (??2) of first unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a first trench structure including a first electrode embedded in a first trench formed in the main surface, and the second system transistor includes a second composite cell which is arranged so as to be adjacent to the first composite cell and constituted of a ?-number (??2) of second unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a second trench structure including a second electrode embedded in a second trench formed in the main surface.

Abstract: A semiconductor device includes a main transistor which includes a first system transistor generating a first system current and a second system transistor generating a second system current independently of the first system transistor and which generates an output current including the first system current and the second system current, a first system monitor transistor which generates a first system monitor current that corresponds to the first system current, and a second system monitor transistor which generates a second system monitor current that corresponds to the second system current.

Abstract: A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.

Abstract: A semiconductor device includes a semiconductor chip that has a main surface, and a field insulating film that partially covers the main surface and has an insulating side wall in which an inclined angle made with the main surface is not less than 20° and not more than 40°.

Abstract: A semiconductor device includes: a semiconductor layer having a partitioned region partitioned by a trench; a field insulating layer which is formed on a main surface of the semiconductor layer at an interval from the trench toward an inner side of the partitioned region and covers the partitioned region; a trench insulating layer formed at least in the trench; an intermediate region annularly formed between the field insulating layer on the main surface of the semiconductor layer and the trench insulating layer; and a bridge insulating layer which is formed in the intermediate region and connects the field insulating layer and the trench insulating layer, wherein the bridge insulating layer has a bridge buried portion buried in the main surface of the semiconductor layer.

Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.

Abstract: A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.

Abstract: A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

Abstract: A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.