Abstract: A microcomputer having a function for monitoring internal resources closed within the microcomputer without preventing an execution of the microcomputer. An address of a register within the microcomputer is determined in advance from the outside of the microcomputer, and at a coincident timing with the register address outputted onto an internal register address bus, data on an internal data bus are taken in and are outputted to the outside of the microcomputer via a serial interface. The information of the internal resources closed within the microcomputer can be obtained without stopping the execution of the microcomputer to enable avoiding of a runaway or trouble of a machine to be controlled by the microcomputer and to enable developing at a real time similar to an execution time.

Abstract: A data processing system is provided which includes a central processing unit connected to a memory and a plurality of peripheral units. When a single peripheral request is issued from one of the plurality of peripheral units for a processing which includes a process to be executed a plurality of times, an interrupt control section which holds mode information indicating whether the currently set mode is a Macro Service processing mode, outputs the mode information in response to the peripheral request issued from the peripheral unit. An execution section which is contained in the central processing unit executes the processing while determining whether the process is completed for a predetermined number of cycles in a state suspending at least a program counter and program status word without saving them in the stack, when the mode information indicates the Macro Service processing mode.

Abstract: A microcomputer includes an internal register previously written with an address from an external of the microcomputer. When the address becomes coincident with a register address outputted on an internal register address bus, data on an internal data bus is fetched to a holding register. A content of the holding register is outputted through a serial interface to the external of the microcomputer. Therefore, it is possible to obtain information of an internal resource of the microcomputer which would otherwise not be outputted from the external of the microcomputer, without stopping the execution of the microcomputer even temporarily. Accordingly, a machine controlled by the microcomputer will not run uncontrollably or break down. Furthermore, since the microcomputer is not stopped, it is possible to develop real time information of the actual application.

Abstract: In a data processor including a serial interface, the serial interface internally includes a transmission end flag formed of a RS flipflop which set in response to the starting of the transmission of data of one byte and reset in response to completion of the transmission of the data of one byte. When the operation is changed from a macroservice processing for a serial data transmission to a vector interrupt processing, a CPU watches and discriminates the condition of the transmission end flag in a programmed operation of the CPU, thereby detecting a timing where data to be transmitted is transferred to a transmission shift register in the serial interface.

Abstract: A semiconductor integrated circuit is provided with a terminal functioning as a port terminal and a pulse circuit terminal, a port mode control register for storing data designating whether the terminal should function as the port terminal or the pulse circuit terminal, a port register for holding data to be externally output, a pulse circuit for outputting a pulse signal, a selector for supplying one of the outputs from the port register and the pulse circuit in response to the value held in the port mode control register, and a switching circuit coupled to the selector and set by a signal for writing data in the port register, for causing the selector to select the output from the port register regardless of the output from the port mode control register.

Abstract: In a microcomputer including a processor, a data memory and a controller for controlling the processor and the data memory, the data memory includes a adaptivity degree data group indicative of the adaptivity degree to the fuzzy set, and an area for storing the result of processing. The processor includes an adaptivity degree data pointer, a result store area pointer, a conformity degree data storing register, and a processing number count register. The microcomputer internally includes a fuzzy inference exclusive-instruction, which causes to compare data in the conformity degree data storing register with data designated by the adaptivity degree data pointer, so as to select a smaller one, and compare the selected dam with data designated by the result store area pointer, so as to store a large one at the area for storing the result of processing, designated by the the result store area pointer.

Abstract: A multiprocessor system includes first and second microcomputers, a address decoding mechanism, and a ready signalling device. The address decoder is coupled to an address bus, to decode address information transferred by the second microcomputer, and supplies a request signal to a request signal input terminal of the first microcomputer. A bus control unit of the first microcomputer responds to the request signal to detect whether an internal bus of the first microcomputer is free from being used by the CPU, and outputs an acknowledge signal to an acknowledge signal output terminal when the internal bus is free. The ready signaling device is coupled to the acknowledge signal output terminal to supply the ready signal to a ready signal input terminal of the second microcomputer in response to the acknowledge signal outputted at the acknowledge signal output terminal and the request signal.

Abstract: The invention provides a pulse generating circuit including a single timer or counter which conducts both a event base count and a subsequent time base count according to clock signals about the event and time base counts, any one of which is selected by a selector. A pulse signal is generated from a RS flip-flop circuit. When the time base count follows the event base count, during the event base count, the output signal from the flip-flop is a 0 signal. During the time base count, the output signal from the flip-flop is a 1 signal. The event base count defines a delay of a pulse generated from RS flip-flop circuit and the time base count defines a width of the pulse.

Abstract: A macroservice engine is provided to exclusively carry out a sequence control in a processing of a macroservice. On the other hand, a command execution unit carries out no macroservice, but generates a bus cycle exciting request for a bus control unit, when an access request signal is generated to access a memory or peripheral registers included in a microcomputer. Thus, a processing of interruption is carried out with high speed, and a burden of a central processing unit is relieved in an interruption process.

Abstract: An apparatus for processing a plurality of tasks comprises a central processing unit (CPU) equipped with a microprogram memory, and a memory. A processing demand to the real time OS required for the execution of the multitask processing is treated as exclusive instruction. For this purpose, the system includes a decoder for decoding the exclusive instruction, and the CPU or the memory has a microprogram for the realization of the instruction.

Abstract: A CPU includes a program counter, an execution unit, and a program status word register. A pulse producing unit connected to the CPU includes a plurality of output terminals, a port selection register for designating at least one of the output terminals, and a system for generating a pulse start timing signal, a system responsive to the pulse start timing signal for bringing the designated output terminal into one of two bistable logic states. A counter counts a clock pulse signal and brings the selected output terminal into the other of the bistable logic states when the counter indicates a predetermined elapsed time. Another system responsive to the pulse start timing signal sends a signal to the CPU requesting a macro service operation.

Abstract: A device for injecting a fixed quantity of sample liquid is provided with a unit for aspirating and injecting sample liquid. The sample aspirating and injection unit has a nozzle connecting portion. The liquid injection device is provided with an injection nozzle attached to and detachable from the nozzle connecting portion of the sample aspirating and injecting unit and electrodes are attached to the injection nozzle. Conductive members which are electrically connected to the electrodes of the injection nozzle are attached to the nozzle connecting portion of the sample aspirating and injecting unit, and a detecting unit which cooperates with the electrodes to detect the surface level of sample liquid is connected to the conductive members.

Abstract: A data processor includes a CPU and an A/D converter for converting one of several analog inputs into digital data. A data memory stores data designating analog inputs to be converted. A circuit, responsive to an A/D conversion completion signal from the A/D converter, supplies a macro service operation request to the CPU, which interrupts the CPU without having to save the contents of a CPU program counter and a CPU status register. Upon completion of the A/D conversion, the converted digital data are stored in a predetermined location, and CPU execution resumes.

Abstract: A method of performing measurement of a hematocrit value and separate sampling of plasma and blood cells, simultaneously. A probe including a pair of detection electrodes each in the form of a suction nozzle, is lowered from a certain initial height into a sample vessel containing blood that has bveen separated into an upper plasma layer and a lower blood cell layer, while the probe travel distance is monitored. When the detection electrodes touch the surface of the plasma layer, the plasma is sampled into a corresponding sampling vessel through one of the electrode suction nozzles. The probe is then lowered further until the electrodes touch the surface of the blood cell layer, and the blood cells are sampled into a different sampling vessel through the other one of the suction nozzles.

Abstract: An automatic analyzing apparatus for analyzing agglutination patterns produced in response to an immunological agglutinating reaction is disclosed. The apparatus comprises a device for carrying a plurality of sample tubes which accommodate blood samples to be analyzed therein at a delivery position in order, a device for forming a plurality of diluent blood samples by diluting the blood samples in the tubes at the delivery position, and a device for transporting microplates having blood samples and reagents delivered in the reaction vessels along the line in a substantially stationary manner.

Abstract: A sample and a reagent are delivered into a reaction vessel having a plurality of inclined bottom surface portions, inclination angles of these portions being increased in a step-wise manner. The reaction vessel is kept still for such a time period that particles descend on the bottom surface portions to form particle patterns. The particle patterns thus formed on respective bottom surface portions are separately detected to produce agglutination and non-agglutination signals. The antigen-antibody reaction is judged in accordance with the agglutination and non-agglutination signals.

Abstract: An apparatus for analyzing blood samples by detecting particle agglutination patterns formed on inclined bottom surfaces of reaction vessels formed in a microplate includes a diluted sample preparing section for delivering given amounts of blood cells and serum contained in a sample tube into diluting vessels mounted on a sample plate secured on a rotating endless belt and for discharging predetermined amount of a diluent into the diluting vessels to form diluted blood cell and serum samples, a diluted sample delivering section for delivering given amounts of the diluted blood cell and serum samples contained in the diluting vessels into an array of reaction vessels of the microplate in a selective manner according to test-items to be analyzed and a reagent delivering section for discharging given reagents into the reaction vessels.

Abstract: A sample and a reagent are delivered into a reaction vessel having a plurality of inclined bottom surface portions, inclination angles of these portions being increased in a step-wise manner. The reaction vessel is kept still for such a time period that particles descend on the bottom surface portions to from particle patterns. The particle patterns thus formed on respective bottom surface portions are separately detected to produce agglutination and non-agglutination signals. The antigen-antibody reaction is judged in accordance with the agglutination and non-agglutination signals.