Abstract: A memory circuit arrangement employing one-transistor-per-bit memory cells in which differential sense amplifiers are utilized for detecting the state of the stored bits. First and second digit lines are arranged substantially parallel to and adjacent to each other and first and second parallel word lines are arranged substantially at right angles to the digit lines. Memory cells are connected at each cross point between the digit lines and the word lines.

Abstract: A memory circuit includes a plurality of memory cells arranged in an array of intersecting rows and columns and a plurality of differential amplifiers corresponding to the number of columns in the array. The memory array is divided into first and second row groups. Each of the differential amplifiers has one input connected to the memory cells in one of the row groups in one of the columns, and a second input connected to the memory cells in the second row group and to the same column connected to the first input. An output sense amplifier has one input selectively connected to the first input of a selected differential amplifier, and a second input selectively connected to a second input of the selected differential amplifier.

Abstract: A memory circuit employing insulated-gate field-effect transistors includes a first circuit for generating a signal upon the completion of one of the circuit functions involved in the operation of the memory circuit. That signal is applied to a second circuit which thereupon produces a timing signal that is used to control a second circuit function of the memory circuit.