Patents by Inventor Hajime Soga
Hajime Soga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080181975Abstract: This invention provides a vasoprotective agent containing a plant or its extract as an effective ingredient. The plant is selected from the group consisting of rosemary, sage, geranium herb, adlai, field horsetail, bitter orange peel, fucus, burdock, dokudami, Japan pepper, Ophiopogon tuber, ginkgo, natsume and dishcloth gourd.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: Kao CorporationInventors: Naonobu Yoshizuka, Yuko Fukuda, Yasuko Amano, Minoru Takizawa, Hajime Soga, Shinobu Mori, Akira Hachiya
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Patent number: 7354829Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.Type: GrantFiled: October 28, 2004Date of Patent: April 8, 2008Assignee: DENSO CORPORATIONInventors: Takaaki Aoki, Yutaka Tomatsu, Akira Kuroyanagi, Mikimasa Suzuki, Hajime Soga
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Publication number: 20050090060Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.Type: ApplicationFiled: October 28, 2004Publication date: April 28, 2005Inventors: Takaaki Aoki, Yutaka Tomatsu, Akira Kuroyanagi, Mikimasa Suzuki, Hajime Soga, Takafumi Arakawa, Yukio Tsuzuki
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Patent number: 6521538Abstract: In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.Type: GrantFiled: February 23, 2001Date of Patent: February 18, 2003Assignee: Denso CorporationInventors: Hajime Soga, Kenji Kondo, Eiji Ishikawa, Yoshikazu Sakano, Mikimasa Suzuki
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Patent number: 6482701Abstract: A method of manufacturing a trench gate type IGBT element, which can sufficiently round off a corner at a bottom of a trench with restricting silicon from being excessively etched. A trench is formed at a surface of a P+-type monocrystalline silicon substrate by conducting an anisotropic etching (STEP 1). A corner portion at a bottom of the trench is formed to a concave shape surface by conducting a concave etching (STEP 2). The concave etching etches the silicon substrate so that a diameter of the trench is gradually reduced as the etching advances. After that, the corner portion at a bottom of the trench is rounded off by conducting an isotropic etching (STEP 3). Since the corner portion is chamfered, a radius of curvature of the corner portion of the bottom of the trench can be increased even if an amount of the etching using the isotropic etching in the STEP 3 is small.Type: GrantFiled: August 2, 2000Date of Patent: November 19, 2002Assignee: Denso CorporationInventors: Eiji Ishikawa, Kenji Kondo, Hajime Soga
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Publication number: 20020167046Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.Type: ApplicationFiled: June 20, 2002Publication date: November 14, 2002Inventors: Takaaki Aoki, Yutaka Tomatsu, Akira Kuroyanagi, Mikimasa Suzuki, Hajime Soga, Takafumi Arakawa, Yukio Tsuzuki
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Patent number: 6469345Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.Type: GrantFiled: January 12, 2001Date of Patent: October 22, 2002Assignee: Denso CorporationInventors: Takaaki Aoki, Yutaka Tomatsu, Akira Kuroyanagi, Mikimasa Suzuki, Hajime Soga
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Publication number: 20010023960Abstract: In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.Type: ApplicationFiled: February 23, 2001Publication date: September 27, 2001Inventors: Hajime Soga, Kenji Kondo, Eiji Ishikawa, Yoshikazu Sakano, Mikimasa Suzuki
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Patent number: 6274452Abstract: After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.Type: GrantFiled: November 5, 1997Date of Patent: August 14, 2001Assignee: Denso CorporationInventors: Shoji Miura, Satoshi Shiraki, Hajime Soga
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Publication number: 20010008291Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.Type: ApplicationFiled: January 12, 2001Publication date: July 19, 2001Inventors: Takaaki Aoki, Yutaka Tomatsu, Akira Kuroyanagi, Mikimasa Suzuki, Hajime Soga
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Patent number: 6165862Abstract: After a CrSiN film and a TiW film are formed on a substrate through an intermediate insulating layer, a mask pattern is formed on the TiW film. Then a two-step dry etching treatment is performed to etch the TiW film and the CrSiN film into a specific shape. Specifically, first the TiW film is selectively etched under conditions including a large content of fluorine radicals. Then the CrSiN film is selectively etched under conditions including a large content of oxygen radicals. Accordingly, a thin film resistor can be formed with high accuracy with respect to the mask pattern.Type: GrantFiled: August 28, 1998Date of Patent: December 26, 2000Assignee: Denso CorporationInventors: Eizi Ishikawa, Kenji Kondo, Hajime Soga
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Patent number: 6090718Abstract: After performing an etching process with respect to one substrate, the substrate is taken out from an etching chamber. Then, a dummy substrate is disposed in the etching chamber and a cleaning process is performed. The cleaning process includes a cleaning step for etching reaction products produced during the etching process to be removed, a seasoning step for adjusting the atmosphere within the etching chamber and the temperature of the substrate, and a purge step for removing suspended foreign materials without generating plasma. By performing the cleaning process, the successive etching process can be performed without generating any black silicon on the substrate, thereby attaining a high production yield.Type: GrantFiled: December 17, 1997Date of Patent: July 18, 2000Assignee: Denso CorporationInventors: Hajime Soga, Kenji Kondo, Eiji Ishikawa, Yoshikazu Sakano, Yuji Ichikawa
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Patent number: 5871659Abstract: A process for dry etching a silicon substrate, in which a mask exposing a region of the surface of the silicon substrate is formed, and the exposed region is dry etched. The dry etching is performed with a gas mixture including chlorine or a chlorine-containing gas, an oxygen-containing gas, and a fluorine-containing gas in which a ratio of a flow rate of oxygen gas to a flow rate of chlorine gas, O.sub.2 /Cl.sub.2, is selected to be from 0.6 to 3. The gas mixture may also contain a fluorine-containing gas and helium. Preferably, the gas mixture excludes carbon-containing gases. The dry etching process allows for an increased etch rate, as well as a high etch selectivity compared to that of SiO.sub.2 gas. The trench formed in the substrate by this process can be made of a larger depth with high reproducibility and good configuration. The sidewall profile angle of the trench is maintained slightly tapered, with a sidewall profile angle of approximately 90 degrees.Type: GrantFiled: June 18, 1996Date of Patent: February 16, 1999Assignee: Nippondenso Co., Ltd.Inventors: Yoshikazu Sakano, Kenji Kondo, Hajime Soga, Yasuo Ishihara, Yoshifumi Okabe
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Patent number: 4912451Abstract: The heterojunction magnetic field sensor is basically a heterojunction structure forming a two-dimensional electron gas layer having a high carrier mobility at the junction portion of at least two different kinds of semiconductor layers having a different band gap, respectively, and further, at least one semiconductor layer having a quantum well structure is provided adjacent to and in contact with the two dimensional electron gas layer, the energy level of the ground state subband thereof being higher than that of the two-dimensional electron gas layer. This heterojunction magnetic field sensor has a high sensitivity which is not saturated even under a high electric field and provides an enhanced output even under the high electric field.Type: GrantFiled: December 29, 1988Date of Patent: March 27, 1990Assignees: Nippon Soken, Inc., Director-General of Agency of Industrial Science and TechnologyInventors: Yoshinobu Sugiyama, Munecazu Tacano, Hajime Soga