Abstract: A micro-relay switch array may comprise an array of micro-relays disposed on a substrate, and a cap disposed over the array of micro-relays, thereby encapsulating the array of micro-relays. The micro-relay switch array may further comprise an array of through-substrate vias (TSVs) associated with the array of micro-relays, arranged such that columns of TSVs alternate with columns of micro-relays, and a plurality of device electrical conductors, each of which electrically couples one of the TSVs of the array of TSVs directly to at least two of the micro-relays. The micro-relay switch array may further comprise a plurality of TSV electrical conductors, each of which electrically couples at least two TSVs together. Each micro-relay of the array of micro-relays may be a micro-electromechanical system (MEMS) switch. The substrate and cap may be glass, and the TSVs may be through-glass vias.

Abstract: Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.

Abstract: Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.