Patents by Inventor Hajime Wada

Hajime Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9240386
    Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 19, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hajime Wada
  • Patent number: 9038932
    Abstract: In accordance with the present invention, there is provided an apparatus for fuelizing inflammable waste capable of efficiently fuelizing inflammable waste while reducing facility and operation costs of the overall system and maintaining stable operation, and so on. More particularly, the apparatus 1 for fuelizing inflammable waste comprises: a primary crusher 4 for crushing an inflammable waste W containing as principal component at least one selected from a group comprising plastics, sponges, fibers, rubbers and wood materials; a foreign matter removing device 7 for removing foreign matters F contained in the crushed objects W1; a secondary crusher 9 for secondarily crushing the crushed objects W3 from which foreign matters I, M are removed; and an injecting device 11 for injecting the secondarily crushed objects W4 generated by the secondary crusher 9 into a burner 10, and so on.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 26, 2015
    Assignee: Taiheiyo Cement Corporation
    Inventors: Shinichiro Saito, Hajime Wada
  • Publication number: 20150140802
    Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventor: Hajime Wada
  • Patent number: 8978489
    Abstract: Provided is a combustion gas bleeding probe, which is elongated in lifetime and improved in chlorine removing ability and so on. The combustion gas bleeding probe (1) comprises a cold gas discharge means having a plurality of discharge ports (2b) for discharging cold gases (C) substantially perpendicularly of the suction direction (S) of a combustion gas (G) and toward the center of the combustion gas flow. A vector (A), which is composed of momentum vectors (MVs) of the cold gas (C) discharged individually from the plural discharge ports, has a vertically downward component. This vertically downward component of the synthesized vector is made the larger, as the angle between the suction direction of the combustion gas and the flow direction of the combustion gas before sucked by the probe becomes the closer to a right angle.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 17, 2015
    Assignee: Taiheiyo Cement Corporation
    Inventors: Hajime Wada, Shinichiro Saito
  • Patent number: 8970007
    Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hajime Wada
  • Publication number: 20110147500
    Abstract: In accordance with the present invention, there is provided an apparatus for fuelizing inflammable waste capable of efficiently fuelizing inflammable waste while reducing facility and operation costs of the overall system and maintaining stable operation, and so on. More particularly, the apparatus 1 for fuelizing inflammable waste comprises: a primary crusher 4 for crushing an inflammable waste W containing as principal component at least one selected from a group comprising plastics, sponges, fibers, rubbers and wood materials; a foreign matter removing device 7 for removing foreign matters F contained in the crushed objects W1; a secondary crusher 9 for secondarily crushing the crushed objects W3 from which foreign matters I, M are removed; and an injecting device 11 for injecting the secondarily crushed objects W4 generated by the secondary crusher 9 into a burner 10, and so on.
    Type: Application
    Filed: August 5, 2009
    Publication date: June 23, 2011
    Applicant: TAIHEIYO CEMENT CORPORATION
    Inventors: Shinichiro Saito, Hajime Wada
  • Publication number: 20110094974
    Abstract: An object is to provide a method and a device for cleaning a filter cloth of a filter press dewaterer that are capable of restoring a filter cloth by effectively cleaning the filter cloth while saving the amount of water used for cleaning without using an acid which requires wastewater treatment. The method is for cleaning a filter cloth of a filter press dewaterer, which dewaters a slurry containing a calcium component, with any one of water, steam, and a mixture thereof. The filter cloth is cleaned by spraying, on the filter cloth to which a tension of 10 to 2000 N/5 cm is applied, any one of: water with a temperature of 100 to 140° C. and a pressure of 50 to 200 kg/cm2; steam with a temperature of 100 to 140° C.; and a mixture thereof.
    Type: Application
    Filed: July 6, 2009
    Publication date: April 28, 2011
    Inventors: Masahiko Katakura, Takao Suzuki, Tomomichi Nakamura, Hajime Wada
  • Patent number: 7928515
    Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masayoshi Asano, Yoshiyuki Suzuki, Tetsuya Ito, Hajime Wada
  • Publication number: 20110041586
    Abstract: Provided is a combustion gas bleeding probe, which is elongated in lifetime and improved in chlorine removing ability and so on. The combustion gas bleeding probe (1) comprises a cold gas discharge means having a plurality of discharge ports (2b) for discharging cold gases (C) substantially perpendicularly of the suction direction (S) of a combustion gas (G) and toward the center of the combustion gas flow. A vector (A), which is composed of momentum vectors (MVs) of the cold gas (C) discharged individually from the plural discharge ports, has a vertically downward component. This vertically downward component of the synthesized vector is made the larger, as the angle between the suction direction of the combustion gas and the flow direction of the combustion gas before sucked by the probe becomes the closer to a right angle.
    Type: Application
    Filed: March 5, 2009
    Publication date: February 24, 2011
    Inventors: Hajime Wada, Shinichiro Saito
  • Patent number: 7842353
    Abstract: A process for manufacturing electrodes for electrolysis, including steps of forming an arc ion plating (AIP) undercoating layer including valve metal or valve metal alloy containing a crystalline tantalum component and a crystalline titanium component on a surface of the electrode substrate comprising valve metal or valve metal alloy, by an arc ion plating method; heat sintering, including the steps of coating a metal compound solution, which includes valve metal as a chief element, onto the surface of the AIP undercoating layer, followed by heat sintering to transform only the tantalum component of the AIP undercoating layer into an amorphous substance, and to form an oxide interlayer, which includes a valve metal oxides component as a chief element, on the surface of the AIP undercoating layer containing the transformed amorphous tantalum component and the crystalline titanium component; and forming an electrode catalyst layer on the surface of the oxide interlayer.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 30, 2010
    Assignee: Permelec Electrode Ltd.
    Inventors: Yi Cao, Hajime Wada, Masashi Hosonuma
  • Patent number: 7837963
    Abstract: A method to efficiently reduce lead content of cement without exerting influence upon quality of the cement. The method comprises the steps of: controlling O2 concentration of combustion gas in an inlet end of a cement kiln to 5% or lower and/or CO concentration thereof 1000 ppm or more; extracting a part of combustion gas from the cement kiln and collecting dust contained in the combustion gas; and collecting lead from the dust collected. With this, the area where raw material temperature in the cement kiln is between 800° and 1100° can be turned into reducing atmosphere to sharply increase volatilization rate of lead, and collection of lead from the dust allows lead content of cement to efficiently be reduced without exerting influence upon quality of the cement.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiheiyo Cement Corporation
    Inventors: Junichi Terasaki, Hajime Wada, Takahiro Hayashida, Soichiro Okamura
  • Patent number: 7771038
    Abstract: A printing apparatus is provided. The printing apparatus forms a dot in a desired position of a printing sheet by ejecting an ink droplet from a nozzle. A static electricity eliminating mechanism eliminates static electricity generated on the printing sheet by a conductive portion that is arranged in a position to which the ink droplet is ejected from the nozzle or an upstream side of such position on a path through which the printing sheet passes. The conductive portion is formed in at least one of a sheet feed roller and an idle roller that carry the printing sheet. The sheet feed roller or the idle roller is formed by coating a predetermined insulating coating on a surface of a conductive rod-shaped member. The conductive portion is formed by stripping off a part of the coating on the sheet feed roller or the idle roller.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: August 10, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Midori Araya, Keisuke Haba, Hajime Wada, Naruhiko Katagiri, Yu Shinagawa
  • Publication number: 20090304565
    Abstract: A method to efficiently reduce lead content of cement without exerting influence upon quality of the cement. The method comprises the steps of: controlling O2 concentration of combustion gas in an inlet end of a cement kiln to 5% or lower and/or CO concentration thereof 1000 ppm or more; extracting a part of combustion gas from the cement kiln and collecting dust contained in the combustion gas; and collecting lead from the dust collected. With this, the area where raw material temperature in the cement kiln is between 800° and 1100° can be turned into reducing atmosphere to sharply increase volatilization rate of lead, and collection of lead from the dust allows lead content of cement to efficiently be reduced without exerting influence upon quality of the cement.
    Type: Application
    Filed: October 19, 2007
    Publication date: December 10, 2009
    Inventors: Junichi Terasaki, Hajime Wada, Takahiro Hayashida, Soichiro Okamura
  • Publication number: 20090242417
    Abstract: A process for manufacturing electrodes for electrolysis, including steps of forming an arc ion plating (AIP) undercoating layer including valve metal or valve metal alloy containing a crystalline tantalum component and a crystalline titanium component on a surface of the electrode substrate comprising valve metal or valve metal alloy, by an arc ion plating method; heat sintering, including the steps of coating a metal compound solution, which includes valve metal as a chief element, onto the surface of the AIP undercoating layer, followed by heat sintering to transform only the tantalum component of the AIP undercoating layer into an amorphous substance, and to form an oxide interlayer, which includes a valve metal oxides component as a chief element, on the surface of the AIP undercoating layer containing the transformed amorphous tantalum component and the crystalline titanium component; and forming an electrode catalyst layer on the surface of the oxide interlayer.
    Type: Application
    Filed: March 18, 2009
    Publication date: October 1, 2009
    Applicant: Permelec Electrode Ltd.
    Inventors: Yi Cao, Hajime Wada, Masashi Hosonuma
  • Publication number: 20080315319
    Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masayoshi ASANO, Yoshiyuki SUZUKI, Tetsuya ITO, Hajime WADA
  • Publication number: 20080299739
    Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates.
    Type: Application
    Filed: May 9, 2008
    Publication date: December 4, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kazutaka YOSHIZAWA, Toru ANEZAKI, Katsuaki OOKOSHI, Teruki MORISHITA, Hajime WADA
  • Patent number: 7379862
    Abstract: A method and apparatus for analyzing and debugging natural language parses is provided. An input sentence is received and parsed by a parsing engine. A table of constituents is retrieved from the parsing engine and a grid tree is drawn representing the input sentence. Nodes of the tree, or connecting points, appear at intersections of the tree “branches.” Once the grid has been drawn, the first syntactically correct parse of the sentence is mapped to the grid in a tree-like manner (the “parse tree”). Input is then received for selecting one of several graphical buttons, for selecting a node that is in the parse tree, for selecting a node that is not in the parse tree, or for selecting options from one of several “pull-down” menus. If a connecting point that is not contained in the parse tree is selected, a group of menu options may be displayed adjacent to the selected connecting point.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: May 27, 2008
    Assignee: Microsoft Corporation
    Inventors: Su Chin Chang, Hajime Wada
  • Patent number: 7320914
    Abstract: A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to form at least one memory cell stack. The memory device is cleaned to remove the mask. A silicide region is formed within the second layer in the at least one memory cell stack, where the silicide region in each memory cell stack is bounded by the spacers.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 22, 2008
    Assignee: Spansion LLC
    Inventors: Hajime Wada, Jaeyong Park
  • Patent number: 7242102
    Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: July 10, 2007
    Assignee: Spansion LLC
    Inventors: Inkuk Kang, Hiroyuki Kinoshita, Boon-Yong Ang, Hajime Wada, Simon S Chan, Cinti X Chen
  • Patent number: 7220643
    Abstract: A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and second layers and the substrate. The dielectric layer is etched to expose at least an upper surface of the memory cell stack. The second layer is etched to recess the second layer with respect to an upper surface of the dielectric layer. A silicide region is formed on the second layer in the memory cell stack, where the silicide region in each memory cell stack is bounded by the dielectric layer extending above the upper surface of the memory cell stack.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Spansion LLC
    Inventors: Hajime Wada, Jaeyong Park, Hirokazu Tokuno, Rinji Sugino