Abstract: A signal processing apparatus includes a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted, and an operation processing part that performs operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format.