Patents by Inventor Hajime Yamagishi
Hajime Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146140Abstract: In this stator, lead wire extended portions and a power wire extended portion are extended from a resin portion by an extended portion separating portion such that the lead wire extended portions are separated from the power wire extended portion by distances that are greater than a maximum value of the width of clearance between an end-side portion of the lead wire extended portion and a facing portion located next to the end-side portion, the resin portion being provided so as to cover lead wire portions and a power wire portion.Type: ApplicationFiled: February 1, 2022Publication date: May 2, 2024Applicants: AISIN CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Toshiya SUGIYAMA, Munehiro TAKAHASHI, Keisuke KIMURA, Ken TAKEDA, Takahito NOZAWA, Takashi MATSUMOTO, Yoshitada YAMAGISHI, Katsuhide KITAGAWA, Hajime KATO
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Publication number: 20240088188Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: September 20, 2023Publication date: March 14, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI
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Patent number: 11908879Abstract: An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.Type: GrantFiled: December 10, 2021Date of Patent: February 20, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hajime Yamagishi
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Publication number: 20230411426Abstract: An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.Type: ApplicationFiled: August 30, 2023Publication date: December 21, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hajime YAMAGISHI
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Publication number: 20230393249Abstract: A sensor device according to the present technology includes: a semiconductor substrate; and a wiring layer part formed on the semiconductor substrate and having a plurality of wiring layers, in which a pixel is disposed in a laminated structure of the semiconductor substrate and the wiring layer part, the pixel including a photoelectric conversion element that performs photoelectric conversion, a first charge holding part and a second charge holding part that hold charges accumulated in the photoelectric conversion element, a first transfer transistor that transfers the charges to the first charge holding part, and a second transfer transistor that transfers the charges to the second charge holding part, and a shield part is disposed to surround each gate wiring line of each of the first and second transfer transistors extending in a thickness direction in the wiring layer part.Type: ApplicationFiled: October 7, 2021Publication date: December 7, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kyohei MIZUTA, Hajime YAMAGISHI
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Patent number: 11817471Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: GrantFiled: August 27, 2021Date of Patent: November 14, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Hajime Yamagishi, Shota Hida, Yuusaku Kobayashi
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Publication number: 20230352512Abstract: The present technique relates to an imaging element, an imaging device, and electronic equipment that enable a wiring capacity and a resistance to be reduced. A semiconductor layer in which pixels including photodiodes, first transfer transistors, and second transfer transistors are arranged in a matrix shape and a wiring layer on the semiconductor layer are included, and a first wiring to which the first transfer transistors of the plurality of pixels arranged in a row direction or a column direction from among the pixels are connected and a second wiring to which the second transfer transistors of the plurality of pixels are connected are included on a side of a second surface of the wiring layer that is opposite to a first surface on which the semiconductor layer is laminated. The present technique can be applied to an imaging element that performs distance measurement, for example.Type: ApplicationFiled: June 21, 2021Publication date: November 2, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA
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Patent number: 11689070Abstract: The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.Type: GrantFiled: May 10, 2021Date of Patent: June 27, 2023Assignee: SONY GROUP CORPORATIONInventor: Hajime Yamagishi
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Publication number: 20220415956Abstract: To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.Type: ApplicationFiled: July 11, 2022Publication date: December 29, 2022Applicant: SONY GROUP CORPORATIONInventors: Hajime YAMAGISHI, Rena KAGAWA, Yuusaku KOBAYASHI, Yutaka NISHIMURA, Makoto HAYAFUCHI, Hayato GOUJI, Natsuhiro AOTA
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Publication number: 20220406827Abstract: The present technology relates to a light receiving element, a distance measurement module, and electronic equipment which are capable of reducing leakage of incident light to adjacent pixels. A light receiving element includes a semiconductor layer in which photodiodes performing photoelectric conversion of infrared rays are formed in units of pixels, and a wiring layer in which a transfer transistor reading charge generated by the photodiodes is formed, and an inter-pixel light shielding unit that shields the infrared rays is formed at a pixel boundary portion of the wiring layer. The present technology can be applied to, for example, a distance measurement module that measures a distance to a subject, and the like.Type: ApplicationFiled: October 16, 2020Publication date: December 22, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yutaro KOMURO, Yoshiki EBIKO, Hajime YAMAGISHI
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Publication number: 20220278160Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: ApplicationFiled: March 15, 2022Publication date: September 1, 2022Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
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Publication number: 20220123039Abstract: An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.Type: ApplicationFiled: December 10, 2021Publication date: April 21, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hajime YAMAGISHI
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Patent number: 11289525Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.Type: GrantFiled: March 11, 2016Date of Patent: March 29, 2022Assignee: Sony CorporationInventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
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Patent number: 11244980Abstract: An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.Type: GrantFiled: June 27, 2018Date of Patent: February 8, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Hajime Yamagishi
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Publication number: 20210391371Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI
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Publication number: 20210351219Abstract: Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.Type: ApplicationFiled: August 2, 2019Publication date: November 11, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Eiji SATO, Akira YAMAZAKI, Takayuki SEKIHARA, Makoto HAYAFUCHI, Syunsuke ISHIZAKI
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Patent number: 11133343Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: GrantFiled: May 2, 2018Date of Patent: September 28, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Hajime Yamagishi, Shota Hida, Yuusaku Kobayashi
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Publication number: 20210265879Abstract: The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventor: HAJIME YAMAGISHI
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Patent number: 11031833Abstract: The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.Type: GrantFiled: December 14, 2018Date of Patent: June 8, 2021Assignee: SONY CORPORATIONInventor: Hajime Yamagishi
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Publication number: 20200243590Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).Type: ApplicationFiled: May 2, 2018Publication date: July 30, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hajime YAMAGISHI, Shota HIDA, Yuusaku KOBAYASHI