Patents by Inventor Hajime Yui

Hajime Yui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110014541
    Abstract: A gas diffusion layer-integrated gasket 1 includes a first gasket 12 which is integrally molded to a periphery of a first gas diffusion layer 11 and a second gasket 14 which is integrally molded to a periphery of a second gas diffusion layer 13, and a hinge part 15 which connects the first gasket 12 and second gasket 14 to each other. The first and second gas diffusion layers sandwich a membrane-electrode assembly 2 in which catalytic electrode layers are provided on both surfaces of an electrolytic membrane from both sides, wherein a seal protrusion 12c is formed on a surface which is in tight contact with the membrane-electrode assembly 2.
    Type: Application
    Filed: June 23, 2010
    Publication date: January 20, 2011
    Applicant: NOK CORPORATION
    Inventors: Hajime Yui, Shigeru Watanabe, Kenichi Oba
  • Patent number: 7662699
    Abstract: An object is to provide a technology capable of improving a manufacturing yield of semiconductor devices by preventing scattering of irregular-shaped scraps formed at the time of dicing. To achieve the above object, for dicing lines, by which an irregular-shaped outer periphery may possibly be cut off, among a plurality of dicing lines, formation of the dicing lines starts from an outside of a semiconductor wafer, and after the semiconductor wafer is cut off partway, formation of the dicing lines is ended before reaching the irregular-shaped outer periphery formed on a outer periphery of the semiconductor wafer. For other dicing lines, formation of the dicing lines starts from the outside of the semiconductor wafer, and after the semiconductor wafer is cut off, is ended outside the semiconductor wafer.
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: February 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hajime Yui, Hisashi Muramatsu
  • Publication number: 20090162993
    Abstract: An object is to provide a technology capable of improving a manufacturing yield of semiconductor devices by preventing scattering of irregular-shaped scraps formed at the time of dicing. To achieve the above object, for dicing lines, by which an irregular-shaped outer periphery may possibly be cut off, among a plurality of dicing lines, formation of the dicing lines starts from an outside of a semiconductor wafer, and after the semiconductor wafer is cut off partway, formation of the dicing lines is ended before reaching the irregular-shaped outer periphery formed on a outer periphery of the semiconductor wafer. For other dicing lines, formation of the dicing lines starts from the outside of the semiconductor wafer, and after the semiconductor wafer is cut off, is ended outside the semiconductor wafer.
    Type: Application
    Filed: November 24, 2005
    Publication date: June 25, 2009
    Inventors: Hajime Yui, Hisashi Muramatsu