Abstract: A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.

Abstract: Disclosed are a memory device and a memory apparatus including the memory device. The memory device may include a first electrode, a second electrode spaced apart from the first electrode, an intermediate layer between the first electrode and the second electrode, and an interface layer in contact with the intermediate layer. The intermediate layer and the interface layer each may have ovonic threshold switching (OTS) characteristics. A material of the interface layer may have a threshold voltage shift greater than a threshold voltage shift (A Vth) of the intermediate layer.

Abstract: Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.

Abstract: A memory element includes a substrate, a first electrode formed on the substrate, a phase-change heterolayer formed on the first electrode and electrically connected to the first electrode, and a second electrode formed on the phase-change heterolayer, wherein the phase-change heterolayer includes one or more confinement material layers and one or more phase-change material layers, and the confinement material layer includes a metal chalcogenide film.

Abstract: A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

Abstract: A chalcogenide material according to one embodiment includes germanium (Ge); arsenic (As); sulfur (S); selenium (Se), and at least one group III metal selected from indium (In), gallium (Ga), and aluminum (Al), wherein the content of the Ge may be greater than about 10 at % and less than or equal to about 30 at %, the content of the As may be greater than about 30 at % and less than or equal to about 50 at %, the content of Se is greater than about 20 at % and less than or equal to about 60 at %, the content of S is greater than about 0.5 at % and less than or equal to about 10 at %, and the content of the group III metal may be in the range of 0.5 at % to 10 at %.

Abstract: Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.

Abstract: Provided are a chalcogenide-based material, and a switching element and a memory device that include the same. The chalcogenide-based material includes: a chalcogenide material and a dopant. The chalcogenide material includes Ge, Sb, and Se. The dopant includes at least one metal or metalloid element selected from In, Al, Sr, and Si, an oxide of the metal or metalloid element, or a nitride of the metal or metalloid element.

Abstract: Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.

Abstract: Provided are a chalcogenide material, and a device and a memory device each including the same. The chalcogenide material may include: germanium (Ge) as a first component; arsenic (As) as a second component; at least one element selected from selenium (Se) and tellurium (Te) as a third component; and at least one element selected from the elements of Groups 2, 16, and 17 of the periodic table as a fourth component, wherein a content of the first component may be from 5 at % to 30 at %, a content of the second component may be from 20 at % to 40 at %, a content of the third component may be from 25 at % to 75 at %, and a content of the fourth component may be from 0.5 at % to 5 at %.

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).