Patents by Inventor Hak-Dong Kim
Hak-Dong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240106222Abstract: An embodiment of the present disclosure provides an arc risk management method comprising: pre-processing measurement values of currents flowing into an electric apparatus; estimating a level of arc energy in the electric apparatus by inputting the measurement values into one artificial intelligence network comprising a first layer including a dilated convolutional neural network and a second layer including a recurrent neural network; and indicating an arc risk to the electric apparatus in a quantitative way according to the level of arc energy.Type: ApplicationFiled: September 12, 2023Publication date: March 28, 2024Applicant: Korea Institute of Energy ResearchInventors: Yoon Dong SUNG, Gi Hwan YOON, Kuk-Yeol BAE, Suk In PARK, Mo Se KANG, Hak Geun JEONG, Hye Jin KIM
-
Publication number: 20230108345Abstract: A system for taking out items wrapped in a packaging film and accommodated in a packaging box with an open top. The system includes a first conveyor configured to transfer a packaging box accommodating items therein, a fixing device for fixing, at a withdrawal position where the items are taken out of the packaging box, the packaging box transferred by the first conveyor with its top open, a withdrawal device for moving to a space in which the items are accommodated in the packaging box so as to suck the same using vacuum suction and take out the same, an item transfer device for transferring the items taken out by the withdrawal device with the items placed on the item transfer device, and a box transfer device for transferring an empty packaging box from which the items are taken out.Type: ApplicationFiled: February 19, 2021Publication date: April 6, 2023Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20230097351Abstract: A packing box folding system, and the packing box folding system including a transfer conveyor on which transfers the packing box from a packing box introducing position to a folded packing box discharging position; a fixed guide panel which extends between the packing box introducing position and the packing box discharging position and is disposed on one side of the transfer conveyor in the width-direction; and a movable suction device which is disposed on the side opposite to the fixed guide panel in the width-direction of the transfer conveyor and is movable between the packing box introducing position and the packing box discharging position, wherein the movable suction device suctions the side surface of the packing box, which faces the side surface in contact with the fixed guide panel, and presses the suctioned side surface inward in the width-direction.Type: ApplicationFiled: February 19, 2021Publication date: March 30, 2023Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20230071621Abstract: An opening system including a cutting device for cutting an adhesive tape; a suctioning and lifting device for suctioning a upper panels, which are separated from each other because the adhesive tape is cut by the cutting device; rod members which are elongated to be inserted into gaps, when the gaps are formed between the upper panels and upper edges of side surfaces in the packaging box because the upper panels are spaced apart from the side panels by the suctioning and lifting device; and an opening device which moves the respective rod members while being in contact with lower surfaces of the upper panels such that the upper panels are rotated outward with respect to boundaries between the upper panels and the side panels.Type: ApplicationFiled: February 19, 2021Publication date: March 9, 2023Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20230074104Abstract: A system for aligning items, which includes a packaging box transfer device to transfer a packaging box accommodating items therein, a fixing device to fix, at a withdrawal position where the items are taken out of the packaging box, the packaging box transferred by the packaging box transfer device with its top open, a withdrawal device to move to a space in which the items are accommodated in the packaging box so as to suck and take out the items, an item transfer device to transfer the items taken out by the withdrawal device with the items placed on the item transfer device, a sensor mounted on the withdrawal device to detect directions of the items taken out by the withdrawal device, and a rotating device to rotate the items taken out by the withdrawal device with the items placed on the rotating device.Type: ApplicationFiled: February 19, 2021Publication date: March 9, 2023Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20230075513Abstract: A reversing system for reversing a packing box, an upper surface of which is opened, and from which products are withdrawn, such that a lower surface of the reversed empty packing box is disposed above. A first conveyor transfers an empty packing box, an upper surface of which is opened, from a position at which products are withdrawn from the packing box to a position at which the packing box is reversed. A turning device holds the packing box to be turned about a horizontal rotation axis, and reverses the packing box. A second conveyor carries the reversed packing box to a position at which the bottom surface is opened. The turning device holds two sides, facing each other, among sides of the packing box, and turns and reverses the packing pox using a portion between the holding locations of the two held sides as a rotation axis.Type: ApplicationFiled: February 19, 2021Publication date: March 9, 2023Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20220411121Abstract: A system for removing a product-packing film from a product having an axis in a longitudinal direction. The packing film surrounds lateral portions of the product. A first end of the packing film surrounding a first longitudinal end of the product is open. A second end of the packing film surrounding a second end of the product opposite the first end of the product is closed. In the system, a conveyor carries a plurality of products each packed with a packing film in a direction perpendicular to the axes of the products while supporting the products such that the axes of the products are parallel to each other. A suction unit draws the first end of the packing film in an axial direction of each of the products. A clamping unit clamps the first end of the packing film drawn by the suction unit.Type: ApplicationFiled: February 19, 2021Publication date: December 29, 2022Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Publication number: 20220411205Abstract: An article withdrawing system for withdrawing articles held in a packing box, the upper surface of which is opened. A first stage holds the packing box carried with the opened upper surface and reverses the packing box so that the articles held in the packing box falls down. A second stage supports and holds the falling-down articles. The first stage includes a support unit supporting and moving the packing box upward and downward, a box holding frame in which the support unit is mounted, a linear movement frame to which the box holding frame is rotatably coupled, a main frame in which the linear movement frame is coupled and supported to be linearly moved and is located and supported on the ground, and a first rotation driving means disposed in the linear movement frame and for rotating and driving the box holding frame.Type: ApplicationFiled: February 19, 2021Publication date: December 29, 2022Inventors: Myung Ho KIM, Sung Woo PARK, Bong Yong SUNG, Hee Dong SON, Dae Hwa KIM, Sun Kyu KIM, Soo Hyun KIM, Hak Dong KIM, In Soo JUNG
-
Patent number: 7662210Abstract: The present invention relates to an apparatus for manufacturing molten irons by injecting fine carbonaceous materials into a melter-gasifier and a method for manufacturing molten irons using the same.Type: GrantFiled: July 29, 2005Date of Patent: February 16, 2010Assignee: POSCOInventors: Young-Chul Kwon, Nam-Suk Hur, Young-Do Park, Hak-Dong Kim
-
Publication number: 20080295647Abstract: The present invention relates to an apparatus for manufacturing molten irons by injecting fine carbonaceous materials into a melter-gasifier and a method for manufacturing molten irons using the same.Type: ApplicationFiled: July 29, 2005Publication date: December 4, 2008Applicant: POSCOInventors: Young-Chul Kwon, Nam-Suk Hur, Young-Do Park, Hak-Dong Kim
-
Publication number: 20080227265Abstract: Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate; forming at least one device isolation layer by depositing an oxide layer in the trench and planarizing the oxide layer; removing the nitride layer and the buffer oxide layer remaining on the high voltage device area; forming a first gate-insulating layer on the high voltage device area; removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and forming a second gate-insulating layer on the low voltage device area.Type: ApplicationFiled: May 30, 2008Publication date: September 18, 2008Inventor: HAK DONG KIM
-
Patent number: 7361562Abstract: Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an oxide layer from a semiconductor substrate; forming a well region in the substrate by performing a first ion implanting process; removing a native oxide layer from the substrate; adjusting a threshold voltage by performing a second ion implanting process on the substrate; and forming a gate oxide layer on the substrate.Type: GrantFiled: December 27, 2004Date of Patent: April 22, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak-Dong Kim
-
Publication number: 20070194376Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.Type: ApplicationFiled: April 20, 2007Publication date: August 23, 2007Inventor: Hak-Dong Kim
-
Patent number: 7259053Abstract: Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.Type: GrantFiled: September 22, 2004Date of Patent: August 21, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak Dong Kim
-
Publication number: 20070187757Abstract: The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.Type: ApplicationFiled: April 10, 2007Publication date: August 16, 2007Inventor: Hak-Dong Kim
-
Patent number: 7253039Abstract: In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.Type: GrantFiled: December 27, 2004Date of Patent: August 7, 2007Assignee: Dongbu Elecotronics Co., Ltd.Inventor: Hak-Dong Kim
-
Patent number: 7223663Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.Type: GrantFiled: December 27, 2004Date of Patent: May 29, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak-Dong Kim
-
Patent number: 7217627Abstract: The present disclosure provides an example of a semiconductor device. In addition, a method for fabricating a semiconductor device is outlined. The semiconductor device may be fabricated by providing a semiconductor substrate, forming a gate over the substrate, forming diffusion barrier ion regions, forming halo regions, forming a source, and forming a drain.Type: GrantFiled: September 17, 2004Date of Patent: May 15, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak-Dong Kim
-
Patent number: 7160783Abstract: A metal oxide semiconductor (MOS) transistor and a method of manufacturing the same are disclosed. An example MOS transistor includes a semiconductor substrate of a first conductivity type where an active region is defined, a gate insulating layer pattern and a gate formed on the active region of the substrate, a spacer formed on side walls of the gate, and source/drain extension regions of a second conductivity type formed within the substrate at both sides of the gate. The example MOS transistor further includes source/drain regions of the second conductivity type formed within the substrate at both side of the spacer and punch-through suppression regions of the first conductivity type formed within the active of the substrate. The punch-through suppression regions surround the source/drain extension regions and the source/drain regions under the gate.Type: GrantFiled: December 27, 2004Date of Patent: January 9, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak-Dong Kim
-
Patent number: 7157357Abstract: Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film pattern stacked sequentially; forming an ion implantation buffer film on an exposed surface of the semiconductor substrate and the gate conductive film pattern; performing a first ion implantation process for injecting fluorine ions into the semiconductor substrate; performing a second ion implantation process for implanting p-type halo ions into the semiconductor substrate; performing a third ion implantation process for implanting n-type impurity ions into the semiconductor substrate; and diffusing the p-type halo ions and the n-type impurity ions using a thermal process.Type: GrantFiled: November 29, 2004Date of Patent: January 2, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hak-Dong Kim