Patents by Inventor Hak Keong Sim
Hak Keong Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220038385Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.Type: ApplicationFiled: October 19, 2021Publication date: February 3, 2022Inventors: Ingo Volkening, Hak Keong Sim, Rush Banerjee
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Patent number: 11153222Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.Type: GrantFiled: May 13, 2019Date of Patent: October 19, 2021Assignee: MaxLinear, Inc.Inventors: Ingo Volkening, Hak Keong Sim, Ritesh Banerjee
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Patent number: 10747538Abstract: An Ethernet device comprises a plurality of Management Data Input/Output (MDIO) Manageable Device (MMD) registers storing Ethernet register field definitions that operate a management interface to one or more MMD devices. An MDIO controller, communicatively coupled to the plurality of MMD registers can control communication via the management interface to the one or more MMD devices based on a mapping of the set of Ethernet register field definitions to the plurality of MMD registers, and dynamically modify the mapping of the set of Ethernet register field definitions to the plurality of MMD registers.Type: GrantFiled: December 21, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Eric Mouchel La Fosse, Paul Louis Chazhoor, Chee Kiang Goh, Hak Keong Sim
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Publication number: 20200201637Abstract: An Ethernet device comprises a plurality of Management Data Input/Output (MDIO) Manageable Device (MMD) registers storing Ethernet register field definitions that operate a management interface to one or more MMD devices. An MDIO controller, communicatively coupled to the plurality of MMD registers can control communication via the management interface to the one or more MMD devices based on a mapping of the set of Ethernet register field definitions to the plurality of MMD registers, and dynamically modify the mapping of the set of Ethernet register field definitions to the plurality of MMD registers.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Eric Mouchel La Fosse, Paul Louis Chazhoor, Chee Kiang Goh, Hak Keong Sim
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Publication number: 20190372905Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.Type: ApplicationFiled: May 13, 2019Publication date: December 5, 2019Inventors: Ingo Volkening, Hak Keong Sim, Ritesh Banerjee
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Patent number: 10326706Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.Type: GrantFiled: May 29, 2015Date of Patent: June 18, 2019Assignee: Lantiq Beteiligungs-GmbH & Co. KGInventors: Ingo Volkening, Hak Keong Sim, Ritesh Banerjee
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Publication number: 20170208015Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.Type: ApplicationFiled: May 29, 2015Publication date: July 20, 2017Applicant: Lantiq Beteiligun-Grmbh & Co. KGInventors: Ingo VOLKENING, Hak Keong SIM, Ritesh BANERJEE
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Patent number: 8588244Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.Type: GrantFiled: October 11, 2011Date of Patent: November 19, 2013Assignee: Lantiq Deutschland GmbHInventors: Shridhar Mubaraq Mishra, Tina Zhang, Chunfeng Hu, Hak Keong Sim
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Publication number: 20120069848Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.Type: ApplicationFiled: October 11, 2011Publication date: March 22, 2012Applicant: Lantiq Deutschland GmbHInventors: Shridhar Mubaraq Mishra, Tina Zhang, Chunfeng Hu, Hak Keong Sim
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Patent number: 8116362Abstract: A line card is proposed in which one or more DMT processing modules 1 communicate with a data link layer platform, such as an ATM, POSPHY or Ethernet processor. The data relating to a single symbol is transmitted between the data link layer platform and a given one of DMT processing modules in a plurality of data portions spaced apart in time. The data portions relating to different channels of a given DMT processing module (or to different DMT processing modules) are interleaved in time. Since the data portions of a given symbol are spaced apart in time, the data relating to a single symbol is transmitted over a longer time period than in conventional devices which reduces the effective burstiness of the traffic, and thus reduces the memory requirements of the data link layer platform.Type: GrantFiled: February 1, 2006Date of Patent: February 14, 2012Assignee: Lantiq Deutschland GmbHInventors: Raj Kumar Jain, Hak Keong Sim
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Patent number: 8064471Abstract: An Ethernet switch has at least one ingress/egress port 1 which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces 3 each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules 5, 7 which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.Type: GrantFiled: September 6, 2002Date of Patent: November 22, 2011Assignee: Lantiq Deutschland GmbHInventors: Shridhar Mubaraq Mishra, Tina Zhang, Chunfeng Hu, Hak Keong Sim
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Patent number: 7802165Abstract: Systems and methods for processing data signals are described. In one implementation, a demodulator and a first decoder unit, such as a convolutional encoder or a quadrature amplitude modulation decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal are provided. The decoded signal may be passed through a de-interleaving unit to form a de-interleaved signal. The first location signal may be passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal may be transmitted to a redundancy decoder, where the signals may be used to perform redundancy decoding.Type: GrantFiled: August 17, 2006Date of Patent: September 21, 2010Assignee: Lantiq Deutschland GmbHInventors: Raj Kumar Jain, Ravindra Singh, Hak Keong Sim
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Patent number: 7743313Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.Type: GrantFiled: August 17, 2006Date of Patent: June 22, 2010Assignee: Lantiq Deutschland GmbHInventors: Raj Kumar Jain, Ravindra Singh, Hak Keong Sim
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Publication number: 20080065968Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a demodulator, a first decoder unit, such as a convolutional encoder or a QAM decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. The decoded signal is passed through a de-interleaving unit to form a de-interleaved signal. The first location signal is passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal are transmitted to a redundancy decoder which employs them to perform redundancy decoding.Type: ApplicationFiled: August 17, 2006Publication date: March 13, 2008Inventors: Raj Kumar Jain, Ravindra Singh, Hak Keong Sim
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Publication number: 20080065969Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.Type: ApplicationFiled: August 17, 2006Publication date: March 13, 2008Inventors: Raj Kumar Jain, Ravindra Singh, Hak Keong Sim
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Publication number: 20080008255Abstract: A discrete multitone (DMT) transceiver communicates with multiple channels generates and receives DMT symbols each having a duration of a timeslot. A transmitter portion of the transceiver includes a symbol processor which generates symbols for multiple channels sequentially, and stores the generated symbols in a buffer until they are transmitted. A receiver portion simultaneously receives symbols on multiple channels and stores the symbols in a buffer, from which the symbols on different channels are read and processed sequentially. To reduce the rate of communication on a given channel, the symbol processors may be idle in respect of some of the timeslots corresponding to that channel. The transceiver may alternatively be an OFDM transceiver.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Inventors: Raj Kumar Jain, Pinxing Lin, Hak Keong Sim, Chee Kiang Goh