Abstract: Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly, portions of a lower package are placed into the recess opening in the substrate of the upper package. The beneficial result is a two-package MSP assembly with a reduced total height. In addition, the size and pitch of solder balls or other joints between the upper package substrate and the lower package substrate may also be reduced.

Abstract: In one aspect, a method of manufacturing a semiconductor package includes providing a semiconductor substrate which includes a plurality of semiconductor chips and a scribe lane defined between the semiconductor chips, forming a trench within the scribe lane, filling the trench with a photolytic polymer, grinding a back side of the semiconductor substrate including the photolytic polymer within the trench, and radiating light onto a front surface of the semiconductor substrate to dissolve the photolytic polymer.

Abstract: An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.