Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Abstract: A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: An display driving circuit including a buffer write controller transmitting a different image frame to a first buffer or a second buffer, a buffer scan controller scanning an image frame stored in the first buffer or the second buffer on the basis of a predetermined cycle, a write signal detector controlling the buffer write controller such that a second image frame is transmitted to the second buffer after a first image frame is transmitted to the first buffer, and a scan buffer switching controller receiving an EOF (End of Frame) command indicating the completion of transmission of the first image frame to the first buffer and controlling the buffer scan controller such that the first image frame stored in the first buffer is scanned after the image frame previously stored in the second buffer is scanned.

Abstract: A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.

Abstract: A memory test system may include a memory apparatus and a test apparatus. The test apparatus may be configured to generate a code distribution of noble cells. The test apparatus may be configured to generate a mass data code distribution and a test result based on the code distribution of noble cells.

Abstract: An display driving circuit including a buffer write controller transmitting a different image frame to a first buffer or a second buffer, a buffer scan controller scanning an image frame stored in the first buffer or the second buffer on the basis of a predetermined cycle, a write signal detector controlling the buffer write controller such that a second image frame is transmitted to the second buffer after a first image frame is transmitted to the first buffer, and a scan buffer switching controller receiving an EOF (End of Frame) command indicating the completion of transmission of the first image frame to the first buffer and controlling the buffer scan controller such that the first image frame stored in the first buffer is scanned after the image frame previously stored in the second buffer is scanned.