Patents by Inventor Hak-Soo Yu
Hak-Soo Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230360693Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar KASIBHATLA, Seong-il O., Hak-soo YU
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Patent number: 11790981Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: GrantFiled: August 8, 2022Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
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Patent number: 11749339Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: GrantFiled: August 8, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
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Publication number: 20230236836Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Inventors: SUKHAN LEE, SHINHAENG KANG, NAMSUNG KIM, SEONGIL O, HAK-SOO YU
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Patent number: 11663008Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.Type: GrantFiled: March 10, 2020Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sukhan Lee, Shinhaeng Kang, Namsung Kim, Seongil O, Hak-Soo Yu
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Patent number: 11635962Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.Type: GrantFiled: March 10, 2020Date of Patent: April 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sukhan Lee, Shinhaeng Kang, Namsung Kim, Seongil O, Hak-Soo Yu
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Patent number: 11620504Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.Type: GrantFiled: June 4, 2020Date of Patent: April 4, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Soo Yu, Nam Sung Kim, Kyomin Sohn, Jaeyoun Youn
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Patent number: 11568907Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.Type: GrantFiled: December 16, 2020Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eldho Pathiyakkara Thombra Mathew, Anirudh Birur Kiran, Hak-Soo Yu, Praful Ramesh Orakkan
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Publication number: 20220383938Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar KASIBHATLA, Seong-Il O, Hak-soo Yu
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Patent number: 11482278Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: GrantFiled: July 7, 2021Date of Patent: October 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
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Publication number: 20220292033Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.Type: ApplicationFiled: February 3, 2022Publication date: September 15, 2022Inventors: Hak-soo YU, Shinhaeng KANG, Yuhwan RO
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Patent number: 11410026Abstract: Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.Type: GrantFiled: November 15, 2018Date of Patent: August 9, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Yeong Cho, Seong-Il O, Hak-Soo Yu, Min-Su Choi
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Publication number: 20220076717Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.Type: ApplicationFiled: December 16, 2020Publication date: March 10, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Eldho Pathiyakkara Thombra Mathew, Anirudh Birur Kiran, Hak-soo Yu, Praful Ramesh Orakkan
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Publication number: 20220036929Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.Type: ApplicationFiled: October 19, 2021Publication date: February 3, 2022Inventors: HAK-SOO YU, NAMSUNG KIM, KYOMIN SOHN, SEONGIL O, SUKHAN LEE
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Publication number: 20210335413Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar KASIBHATLA, Seong-il O, Hak-soo Yu
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Patent number: 11158357Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.Type: GrantFiled: March 10, 2020Date of Patent: October 26, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hak-Soo Yu, Namsung Kim, Kyomin Sohn, Seongil O, Sukhan Lee
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Patent number: 11074961Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.Type: GrantFiled: January 18, 2019Date of Patent: July 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pavan Kumar Kasibhatla, Seong-il O, Hak-soo Yu
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Publication number: 20210150319Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.Type: ApplicationFiled: June 4, 2020Publication date: May 20, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Hak-Soo YU, Nam Sung KIM, Kyomin SOHN, Jaeyoun YOUN
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Publication number: 20200294558Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.Type: ApplicationFiled: March 10, 2020Publication date: September 17, 2020Inventors: HAK-SOO YU, NAMSUNG KIM, KYOMIN SOHN, SEONGIL O, SUKHAN LEE
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Publication number: 20200293319Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.Type: ApplicationFiled: March 10, 2020Publication date: September 17, 2020Inventors: Sukhan Lee, Shinhaeng Kang, Namsung Kim, Seongil O, Hak-Soo Yu