Abstract: Provided is a liquid crystal display to provide improved transmittance and visibility includes a first substrate; a first switching element and a second switching element formed on the first substrate configured to be switched by the same signal; a first subpixel electrode connected to the first switching element; a second subpixel electrode connected to the second switching element; a third switching element connected to the second switching element; a third subpixel electrode connected to the third switching element; a second substrate; a common electrode formed on the second substrate; and a liquid crystal layer formed between the first substrate and the second substrate.

Abstract: A unit pixel of a liquid crystal display panel includes a plurality of domains formed using a photoalignment process technology. The domains have different domain alignment vectors, and major axes of liquid crystal molecules on alignment layers are aligned in parallel to transmission axes of the liquid crystal display panel. In addition, the unit pixel has a pixel electrode including slits. The slits have a slit angle at which the slits cross alignments of the domains at a predetermined angle, and the slit angle is less than 45°. As a result, transmittance of the unit pixel may increase, ensuring high image quality.

Abstract: The present invention relates a liquid crystal display. The liquid crystal display includes a liquid crystal panel assembly including a plurality of pixels arranged in a matrix, a gate driver applying gate signals to the pixels for application of data signals to the pixels, a data driver selecting gray voltages corresponding to gray signals and applying the selected gray voltages to the pixels as the data signals, and a signal controller providing the gray signals and control signals for controlling the gray signals for the gate driver and the data driver. The data signals include normal data signals and a black data signal. The data driver alternately applies the normal data signals and the black data signal to the pixels under control of the signal controller. A scanning direction of the normal data signals is opposite in adjacent frames.

Abstract: A TFT array panel on which both pixel electrodes and common electrodes are formed and a color filter panel is disposed opposing the array panel, and liquid crystals are interposed therebetween. The liquid crystals are aligned parallel to the two panels and driven by parallel electric field formed between the pixel electrodes and reference electrodes. Polarization films are arranged outsides the two panels, and a quasi-A plate compensation film is arranged between the color filter panel and the polarization film.

Abstract: In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors.

Abstract: A liquid crystal display device having a first substrate and a second substrate facing the first substrate, a liquid crystal layer interposed between the first substrate and the second substrate, a pixel electrode formed over the first substrate, a common electrode formed over the first substrate with insulating from the pixel electrode, wherein a portion of the common electrode overlaps with the pixel electrode, includes a gray voltage generator generating a plurality of gray voltages, an image signal modification assembly configured to receive a first image signal, a second image signal, and a third image signal for subsequent three frames and modify the second image signal based on the first image signal and the third image signal, and a data driver configured to provide a data voltage selected from the plurality of gray voltages to the pixel electrode corresponding to the modified signal in the image signal modification assembly.

Abstract: Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween.

Abstract: A display panel is provided. The display panel includes a substrate and a pixel electrode disposed on the substrate and having a pair of first primary edges facing each other and a pair of second primary edges connected to the first primary edges and facing each other, wherein the second primary edges include a plurality of protrusions of the pixel electrode having the shape of sawteeth.

Abstract: In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors.

Abstract: A liquid crystal display includes: a substrate; a pixel electrode disposed on the substrate and having a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of bent edges substantially parallel to each other, the second subpixel electrode has a pair of bent edges substantially parallel to each other, and the second subpixel electrode has a height greater than a height of the first subpixel electrode.

Abstract: A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes.

Abstract: Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween.

Abstract: A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes.

Abstract: In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors.

Abstract: The disclosure describes a liquid crystal display panel including a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels has first and second gray scale regions which are split up and down and have different areas, first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to first and second gray scale regions so that first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven.

Abstract: A liquid crystal display (“LCD”) includes a plurality of gate lines, a plurality of data lines intersecting the gate lines, a plurality of switching elements connected to the gate lines and the data lines, a plurality of storage electrodes, a plurality of storage electrode lines connected to the storage electrodes, a plurality of pixel electrodes connected to the switching elements and overlapping the storage electrodes, a gate driver generating gate signals having a gate-on voltage and a gate-off voltage to apply to the gate lines, a data driver generating data voltages corresponding to externally applied image signals to apply to the data lines, and a storage electrode driver generating storage electrode signals having a reference voltage, a high voltage larger than the reference voltage, and a low voltage smaller than the reference voltage to apply to the storage electrode lines.

Abstract: A liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a common electrode facing the pixel electrode. The first subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to each other, the first oblique edges making an oblique angle with the first edge and the second edge and meeting the first edge. The second subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to or substantially perpendicular to the first oblique edges of the first subpixel electrode, the first oblique edges of the second subpixel electrode meeting the first edge of the second subpixel electrode.

Abstract: A liquid crystal display is provided, which includes: a plurality of pixels; a gray voltage generator generating a plurality of gray voltages; an image signal modifier that receives first, second, and third image signals for a pixel in three successive frames, generates a preliminary signal for the second image signal based on the first image signal, and generates a modified signal for the second image signal based on the preliminary signal and the third image signal; and a data driver converting the modified signal into a data voltage selected from the gray voltages and applying the data voltage to the pixel, wherein a range of the gray voltages is substantially equal to a range of target voltages for obtaining target luminance of the pixel, and a highest available value for the modified signal is equal to a highest available value of the image signals.

Abstract: Provided is a liquid crystal display that includes a first substrate, a second substrate opposite to and facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, wherein the first substrate includes a common electrode, the second substrate includes gate lines disposed on an insulating plate, first and second data lines insulated from and intersecting the gate lines and receiving complementary data signals, a first thin film transistor connected to the first data line, a second thin film transistor connected to the second data line, a first pixel electrode connected to an output terminal of the first thin film transistor, and a second pixel electrode connected to an output terminal of the second thin film transistor, the first pixel electrode has two or more interconnected sub-pixel electrodes, the second pixel electrode has two or more interconnected sub-pixel electrodes, and the sub-pixel electrodes of the first pixel electrode are interdigitated

Abstract: A liquid crystal display (“LCD”) includes a plurality of gate lines, a plurality of data lines intersecting the gate lines, a plurality of switching elements connected to the gate lines and the data lines, a plurality of storage electrodes, a plurality of storage electrode lines connected to the storage electrodes, a plurality of pixel electrodes connected to the switching elements and overlapping the storage electrodes, a gate driver generating gate signals having a gate-on voltage and a gate-off voltage to apply to the gate lines, a data driver generating data voltages corresponding to externally applied image signals to apply to the data lines, and a storage electrode driver generating storage electrode signals having a reference voltage, a high voltage larger than the reference voltage, and a low voltage smaller than the reference voltage to apply to the storage electrode lines.