Abstract: A data processing system that comprises an encoder, and a communication system is disclosed. Compressed data produced by the encoder is decompressed to produce first decompressed data, and a first signature representative of the first decompressed data is generated. Compressed data that has been transferred by the communication system is decompressed to produce second decompressed data, and a second signature representative of the second decompressed data is generated. The first signature and the second signature are compared, and the comparison is used to determine whether an error has occurred.

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

Abstract: A data processing system that comprises a processing unit and a communications bus over which bus transactions to access memory can be performed is disclosed. The system includes a codec, and the processing unit can initiate over the communications bus, bus transactions that comprise the codec accessing the memory.

Abstract: In response to determining circuitry determining that a portion of data to be sent to a recipient over an interconnect has a predetermined value, data sending circuitry performs data elision to: omit sending at least one data FLIT corresponding to the portion of data having the predetermined value; and send a data-elision-specifying FLIT specifying data-elision information indicating to the recipient that sending of the at least one data FLIT has been omitted and that the recipient can proceed assuming the portion of data has the predetermined value. The data-elision-specifying FLIT is a FLIT other than a write request FLIT for initiating a memory write transaction sequence. This helps to conserve data FLIT bandwidth for other data not having the predetermined value.

Abstract: Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

Abstract: When storing data of an array of data in memory in a graphics processing system, respective memory regions are allocated for storing blocks of the data array, with the allocated region of memory for a block of the data array corresponding to a maximum possible size of the block of the data array when compressed, and being divided into a plurality of memory allocation sub-blocks, having at least one sub-block having a first, larger size and at least one sub-block having a second, smaller size. Blocks of the data array are compressed using a compression scheme, with each compressed block being stored in one or more of the sub-blocks of its allocated memory region.

Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.

Abstract: Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

Abstract: When operating a data processing system comprising a data encoder operable to perform a first encoding scheme that is configured for processing sets of data arranged in a first data format, for a plurality of sets of data received in a second, different data format, the bits for at least some of the received plurality of sets of data in the second data format are re-ordered to map the bits for the at least some of the received plurality of sets of data in the second data format into the first arrangement of bits associated with the first data format to thereby generate from the received plurality of sets of data in the second data format one or more sets of data in the first data format for processing using the first encoding scheme.

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

Abstract: When operating a data processing system comprising a data encoder operable to perform a first encoding scheme that is configured for processing sets of data arranged in a first data format, for a plurality of sets of data received in a second, different data format, the bits for at least some of the received plurality of sets of data in the second data format are re-ordered to map the bits for the at least some of the received plurality of sets of data in the second data format into the first arrangement of bits associated with the first data format to thereby generate from the received plurality of sets of data in the second data format one or more sets of data in the first data format for processing using the first encoding scheme.

Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.

Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.

Abstract: When executing a program on a data processor comprising an execution unit for executing instructions in a program to be executed by the data processor, the execution unit being associated with one or more hardware units operable to execute instructions, at least one instruction in a program is associated with an indication of whether the instruction should be issued directly for execution by a hardware unit or should be intercepted during its execution by the execution unit. The execution unit then, when decoding the instruction for execution by a hardware unit in the program, determines from the indication associated with the instruction whether the instruction should be issued directly for execution by a hardware unit or intercepted during its execution by the execution unit, and issues the instruction for execution by a hardware unit directly, or pauses execution of the instruction and performs another operation, accordingly.

Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator. When a request for processing includes protected content, the host processor includes within a command for a command stream, an indication that a subsequent sequence of one or more command(s) within that command stream associated with the protected content is to be implemented by the accelerator in a protected mode of operation. Then, when that command is executed, the accelerator initiates or requests a switch into the protected mode of operation.

Abstract: Apparatuses and methods for address translation invalidation are provided. In an apparatus having address translation storage which stores merged address translation information for multiple address translation stages, a set of counters are provided to hold a set of counter values. Entries in the address translation storage are stored with identifiers of first and second counters selected from the set of counters in dependence on respective context information for a first stage and a second stage of address translation together with a counter value of each counter. In response to an invalidation request specifying a first or second addressing scheme invalidation context a counter of the set of counters is selected in dependence on the first or second addressing scheme invalidation context and its value is modified.

Abstract: A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.

Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.

Abstract: A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Abstract: A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.