Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: A data processing system for processing data messages received from multiple user terminals over one or more data networks includes a processor, an input/output (I/O) range, and multiple processing layers configured to run on the processor. The multiple processing layers include an application layer, including an application, configured when run on the processor to process data messages from the I/O range, a hardware layer configured when run on the processor to communicate with hardware devices including the user terminals, and an operating system kernel layer configured when run on the processor to provide data communications between the application layer and the hardware layer. The application layer can bypass the operating system kernel layer when communicating with the hardware layer to poll the I/O range for data messages for input to and processing by the application.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: An adaptable replica server system includes a primary replica associated with a primary storage for storing information and a primary processor, and a secondary replica associated with a secondary storage and a secondary processor for creating confirmation data upon receiving input data from the primary replica. The replica server system is configurable so as to work as an asynchronous server replica system and/or as a synchronous server replica system depending on an attribute included in the input data.

Abstract: An adaptable replica server system comprising a primary replica being associated with a primary storage for storing information and a primary processing means, and a secondary replica being associated with a secondary storage and a secondary processing means for creating confirmation data upon receiving input data from the primary replica. The replica server system is configurable to work as an asynchronous server replica system and/or as a synchronous server replica system depending on an instruction.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry controls (110, 150) the CPU to poll the I/O range for input to the application. The control circuitry also monitors (120, 160) whether or not each poll results in input to the application and adjusts (140) a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected (130). A control circuitry and a central computer server of an automated exchange system are also provided.

Abstract: Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry controls (110, 150) the CPU to poll the I/O range for input to the application. The control circuitry also monitors (120, 160) whether or not each poll results in input to the application and adjusts (140) a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected (130). A control circuitry and a central computer server of an automated exchange system are also provided.

Abstract: Latency in electronic trading is dramatically reduced by delaying trade order validation until a match or trade can potentially occur. If a new order does not meet the matching criteria for an existing order in an order book, then the new order is stored in the order book without performing validation processing in a first example embodiment. In a second example embodiment, the order is stored in the order book before validation has completed. But if a new order meets matching criteria for an existing order stored in an order book, then order validation processing is performed for both of the matching orders. Once the order validation processing is successfully completed for both of the matching orders, then the trade is executed. Order validation processing includes both risk calculations and account validations, (e.g., checking to ensure the party has the necessary money or collateral if a buyer or is the owner if a seller).

Abstract: Latency in electronic trading is dramatically reduced by delaying trade order validation until a match or trade can potentially occur. If a new order does not meet the matching criteria for an existing order in an order book, then the new order is stored in the order book without performing validation processing in a first example embodiment. In a second example embodiment, the order is stored in the order book before validation has completed. But if a new order meets matching criteria for an existing order stored in an order book, then order validation processing is performed for both of the matching orders. Once the order validation processing is successfully completed for both of the matching orders, then the trade is executed. Order validation processing includes both risk calculations and account validations, (e.g., checking to ensure the party has the necessary money or collateral if a buyer or is the owner if a seller).

Abstract: An instruction, processor, system, and method allow application level software to explicitly request a temporary performance boost, from computing hardware. Advanced management of a working frequency of a processor achieves the performance boost. Preferably, a processor with that advanced management and performance boost is implemented in an electronic exchange or another application where peak periods may occur.

Abstract: An adaptable replica server system comprising a primary replica being associated with a primary storage for storing information and a primary processing means, and a secondary replica being associated with a secondary storage and a secondary processing means for creating confirmation data upon receiving input data from the primary replica, wherein the replica server system is designed to be configurable so as to work as an asynchronous server replica system and/or as a synchronous server replica system depending on an instruction.

Abstract: The invention discloses an instruction, processor, system and method which allow application level software to explicitly request a temporary performance boost, from computing hardware. More specifically it relates to advanced management of working frequency of a processor in order to achieve the performance boost. Preferably a processor according to the invention may be implemented in electronic exchanges or similar applications where peak periods may occur.