Patents by Inventor Hakan Zeffer
Hakan Zeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10462267Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: GrantFiled: May 31, 2016Date of Patent: October 29, 2019Assignee: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Patent number: 9606924Abstract: The exemplary embodiments described herein relate to supporting fast and deterministic execution and simulation in multi-core environments. Specifically, the exemplary embodiments relate to systems and methods for implementing determinism in a memory system of a multithreaded computer. A exemplary system comprises a plurality of processors within a multi-processor environment, a cache memory within the processor and including metadata, and a hardware check unit performing one of a load check and a store check on the metadata to detect a respective one of a load metadata mismatch and a store metadata mismatch, and invoking a runtime software routine to order memory references upon a detection of one of the load metadata mismatch and the store metadata mismatch.Type: GrantFiled: June 22, 2012Date of Patent: March 28, 2017Assignee: Wind River Systems, Inc.Inventor: Hakan Zeffer
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Publication number: 20160277549Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Applicant: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Publication number: 20150215204Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Applicant: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Patent number: 9001828Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: GrantFiled: March 21, 2011Date of Patent: April 7, 2015Assignee: Marvell World Trade Ltd.Inventors: Håkan Zeffer, Jakob Cärlstrom, Pär Westlund, Johan Bäck, Ronny Nilsson
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Publication number: 20130346682Abstract: The exemplary embodiments described herein relate to supporting fast and deterministic execution and simulation in multi-core environments. Specifically, the exemplary embodiments relate to systems and methods for implementing determinism in a memory system of a multithreaded computer. A exemplary system comprises a plurality of processors within a multi-processor environment, a cache memory within the processor and including metadata, and a hardware check unit performing one of a load check and a store check on the metadata to detect a respective one of a load metadata mismatch and a store metadata mismatch, and invoking a runtime software routine to order memory references upon a detection of one of the load metadata mismatch and the store metadata mismatch.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Inventor: Hakan ZEFFER
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Patent number: 8539455Abstract: A system, method, and computer program product that captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted. Reuse distance for one memory operation may be measured as the number of memory operations that have been performed since the memory object it accesses was last accessed. Separate call stacks leading up to the same memory operation are identified and statistics are separated for the different call stacks. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.Type: GrantFiled: March 26, 2008Date of Patent: September 17, 2013Assignee: Rogue Wave Software, Inc.Inventors: Erik Berg, Erik Hagersten, Hakan Zeffer, Magnus Vesterlund, Mats Nilsson, Mikael Petterson
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Patent number: 8443341Abstract: A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.Type: GrantFiled: November 9, 2007Date of Patent: May 14, 2013Assignee: Rogue Wave Software, Inc.Inventors: Erik Berg, Erik Hagersten, Mats Nilsson, Mikael Petterson, Magnus Vesterlund, Hakan Zeffer
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Publication number: 20120243538Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: XELERATED ABInventors: Håkan Zeffer, Jakob Carlström, Pär Westlund, Johan Bäck, Ronny Nilsson
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Patent number: 8141058Abstract: A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations.Type: GrantFiled: June 5, 2007Date of Patent: March 20, 2012Assignee: Rogue Wave Software, Inc.Inventors: Erik Berg, Erik Hagersten, Mats Nilsson, Mikael Petterson, Magnus Vesterlund, Hakan Zeffer
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Publication number: 20090125465Abstract: A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.Type: ApplicationFiled: November 9, 2007Publication date: May 14, 2009Inventors: Erik Berg, Erik Hagersten, Mats Nilsson, Mikael Petterson, Magnus Vesterlund, Hakan Zeffer
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Publication number: 20090055594Abstract: A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations.Type: ApplicationFiled: June 5, 2007Publication date: February 26, 2009Inventors: Erik Berg, Erik Hagersten, Mats Nilsson, Mikael Petterson, Magnus Vesterlund, Hakan Zeffer
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Publication number: 20080244533Abstract: A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Inventors: Erik Berg, Erik Hagersten, Hakan Zeffer, Magnus Vesterlund, Mats Nilsson, Mikael Petterson
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Publication number: 20080010417Abstract: In one embodiment, a method comprises communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation; determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and resolving a conflict between the memory operation and the memory transaction.Type: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Inventors: Hakan Zeffer, Erik Hagersten, Anders Landin, Kevin Moore
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Publication number: 20070260821Abstract: In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.Type: ApplicationFiled: May 4, 2006Publication date: November 8, 2007Applicant: Sun Microsystems, Inc.Inventors: Hakan Zeffer, Anders Landin, Erik Hagersten
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Publication number: 20070255907Abstract: In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicant: Sun Microsystems, Inc.Inventors: Hakan Zeffer, Erik Hagersten, Anders Landin, Shailender Chaudhry, Paul Loewenstein, Robert Cypher, Zoran Radovic
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Publication number: 20070255908Abstract: In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicant: Sun Microsystems, Inc.Inventors: Hakan Zeffer, Erik Hagersten