Abstract: An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines.

Abstract: An image recognition device includes: an image processing device that acquires a feature amount from an image; and an identification device that determines whether a prescribed identification object is present in the image, and identifies the identification object. The identification device includes a BNN that has learned the identification object in advance, and performs identification processing by performing a binary calculation with the BNN on the feature amount acquired by the image processing device. Then, the identification device selects a portion effective for identification from among high-dimensional feature amounts output by the image processing device to reduce the dimensions used in identification processing, and copies low-dimensional feature amounts output by the image processing device to increase dimensions.

Abstract: Electric charges depending on values of N+ electric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N?N+) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of N+ multiplied values obtained by multiplying each of the positive loads by each of the values of the N+ electric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N?N+) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N?N+) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N?N+) multiplied values from the sum of N+ multiplied values.

Abstract: An image recognition device involves successively extracting co-occurrence pairs in synchronization with a clock, setting a weighting for the portion connecting the input layer and the intermediate layer corresponding to the extracted co-occurrence pairs, and successively inputting a first vote to the input layer. Meanwhile, the intermediate layer adds and stores the successively inputted number of votes. By continuing this operation, a value the same as if a histogram were inputted to an input layer is achieved in the intermediate layer, without creating a histogram. In this way, the image recognition device of this embodiment can perform image recognition while avoiding the creation of a histogram, which consumes vast amounts of memory. As a result of this configuration, it is possible to save memory resources, simplify circuits, and improve calculation speed, and achieve an integrated circuit suitable to an image recognition device.

Abstract: An image processing device can use a calculation formula based on an ellipse to approximate a base function of a reference GMM. The burden rate according to a co-occurrence correspondence point can be approximately determined by a calculation in which the Manhattan distance to the ellipse and the co-occurrence correspondence point and the width of the ellipse are input to a calculation formula for the burden rate based on the base function. The width of the ellipse is quantized by the nth power of 2 (where n is an integer of 0 or greater), and the calculation can be carried out by means of a bit shift.

Abstract: An image processing device converts an image that is a recognition object image to high-resolution, medium-resolution, and low-resolution images. The device sets the pixel of interest of the high-resolution image, and votes the co-occurrence in a gradient direction with offset pixels, the co-occurrence in the gradient direction pixels in the medium-resolution image, and the co-occurrence in the gradient direction pixels in the low-resolution image, to a co-occurrence matrix. The device creates such a co-occurrence matrix for each pixel combination and for each resolution. The device executes the process on each of the pixels of the high-resolution image, and creates a co-occurrence histogram wherein the elements of a plurality of co-occurrence matrices are arranged in a line. The device normalizes the co-occurrence histogram and extracts, as a feature quantity of the image, a vector quantity having as a component a frequency resulting from the normalization.

Abstract: A multiply-accumulate operation device, circuit and method are disclosed. In on example, a multiply-accumulate operation device includes input lines, multiplication units, an accumulation unit, a charging unit, and an output unit. Pulse signals having pulse widths corresponding to input values are input to the input lines. The multiplication units generate, based on the pulse signals, charges corresponding to multiplication values obtained by multiplying the input values by weight values. The accumulation unit accumulates a sum of the charges corresponding to the multiplication values. The charging unit charges the accumulation unit at a charging speed associated with its accumulation state. The output unit outputs a multiply-accumulate signal representing a sum of the multiplication values by executing threshold determination using a threshold value associated with the accumulation state of the accumulation unit on a voltage held by the accumulation unit after the charging by the charging unit is started.

Abstract: An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines.

Abstract: A hardware configuration is constructed for calculating at high speed the co-occurrence of luminance gradient directions between differing resolutions for a subject image. In an image processing device, a processing line for high-resolution images, a processing line for medium-resolution images, and a processing line for low-resolution images are arranged in parallel, and the luminance gradient directions are extracted for each pixel simultaneously in parallel from images having the three resolutions. Co-occurrence matrix preparation units prepare co-occurrence matrices by using the luminance gradient directions extracted from these images having the three resolutions, and a histogram preparation unit outputs a histogram as an MRCoHOG feature amount by using these matrices. To concurrently processing the images having the three resolutions, high-speed processing can be performed, and moving pictures output from a camera can be processed in real time.

Abstract: Electric charges depending on values of N+ electric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N?N+) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of N+ multiplied values obtained by multiplying each of the positive loads by each of the values of the N+ electric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N?N+) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N?N+) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N?N+) multiplied values from the sum of N+ multiplied values.

Abstract: Electric charges depending on values of N+ electric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N?N+) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of N+ multiplied values obtained by multiplying each of the positive loads by each of the values of the N+ electric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N?N+) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N?N+) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N?N+) multiplied values from the sum of N+ multiplied values.

Abstract: An image recognition device includes: an image processing device that acquires a feature amount from an image; and an identification device that determines whether a prescribed identification object is present in the image, and identifies the identification object. The identification device includes a BNN that has learned the identification object in advance, and performs identification processing by performing a binary calculation with the BNN on the feature amount acquired by the image processing device. Then, the identification device selects a portion effective for identification from among high-dimensional feature amounts output by the image processing device to reduce the dimensions used in identification processing, and copies low-dimensional feature amounts output by the image processing device to increase dimensions.

Abstract: An image recognition device includes: an image processing device that acquires a feature amount from an image; and an identification device that determines whether a prescribed identification object is present in the image, and identifies the identification object. The identification device includes a BNN that has learned the identification object in advance, and performs identification processing by performing a binary calculation with the BNN on the feature amount acquired by the image processing device. Then, the identification device selects a portion effective for identification from among high-dimensional feature amounts output by the image processing device to reduce the dimensions used in identification processing, and copies low-dimensional feature amounts output by the image processing device to increase dimensions.

Abstract: An image processing device converts an image that is a recognition object image to high-resolution, medium-resolution, and low-resolution images. The device sets the pixel of interest of the high-resolution image, and votes the co-occurrence in a gradient direction with offset pixels, the co-occurrence in the gradient direction pixels in the medium-resolution image, and the co-occurrence in the gradient direction pixels in the low-resolution image, to a co-occurrence matrix. The device creates such a co-occurrence matrix for each pixel combination and for each resolution. The device executes the process on each of the pixels of the high-resolution image, and creates a co-occurrence histogram wherein the elements of a plurality of co-occurrence matrices are arranged in a line. The device normalizes the co-occurrence histogram and extracts, as a feature quantity of the image, a vector quantity having as a component a frequency resulting from the normalization.

Abstract: Electric charges depending on values of N+ electric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N?N+) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of N+ multiplied values obtained by multiplying each of the positive loads by each of the values of the N+ electric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N?N+) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N?N+) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N?N+) multiplied values from the sum of N+ multiplied values.

Abstract: A hardware configuration is constructed for calculating at high speed the co-occurrence of luminance gradient directions between differing resolutions for a subject image. In an image processing device, a processing line for high-resolution images, a processing line for medium-resolution images, and a processing line for low-resolution images are arranged in parallel, and the luminance gradient directions are extracted for each pixel simultaneously in parallel from images having the three resolutions. Co-occurrence matrix preparation units prepare co-occurrence matrices by using the luminance gradient directions extracted from these images having the three resolutions, and a histogram preparation unit outputs a histogram as an MRCoHOG feature amount by using these matrices. To concurrently processing the images having the three resolutions, high-speed processing can be performed, and moving pictures output from a camera can be processed in real time.