Abstract: A dual-port memory controller having a memory controller and at least one delaying unit. Since the memory controller executes a data access by selecting one processor, the memory controller outputs at least one request disapproval signal indicating that it cannot accept data access requests from other processors. The delaying unit includes a clock oscillator, and flip-flops receiving the clock signal and delaying the request disapproval signal. The delaying unit varies the delay time by varying the clock frequency of the clock oscillator. The memory controller executes data access to the same memory area after a predetermined period of time elapses, so processors can read/write stabilized data.

Abstract: A dual-port memory controller having a memory controller and at least one delaying unit. Since the memory controller executes a data access by selecting one processor, the memory controller outputs at least one request disapproval signal indicating that it cannot accept data access requests from other processors. The delaying unit includes a clock oscillator, and flip-flops receiving the clock signal and delaying the request disapproval signal. The delaying unit varies the delay time by varying the clock frequency of the clock oscillator. The memory controller executes data access to the same memory area after a predetermined period of time elapses, so processors can read/write stabilized data.

Abstract: The present invention relates to a counter circuit for counting the rotated position of the motor and controlling absolute position of the same to control an absolute position of a robot system, which comprises, a RS-422 receiver for receiving encode signals from a motor driver, a 16-bit counter device for receiving rotated-number data of the motor supplied from the receiver and counting the data to output the counted value to a CPU via a bus line, a plurality of 4-bit counters for counting the signals when overflow or underflow is produced at the 16-bit counter portion, a first 8-bit latch circuit for receiving the counted values from the 4-bit counters and outputting the counted values to the CPU, and, a second 8-bit latch circuit for controlling the output state of the receiver on the basis of a control signal supplied through the bus line when a zero pulse control signal is inputted for searching an origin of the robot system thereby preventing erroneous counting operations due to a program and reducing t