Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.

Abstract: A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.

Abstract: A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.

Abstract: A semiconductor device may include a substrate including a fin active region extending in a first direction, a gate structure crossing the fin active region and extending in a second direction crossing the first direction, source/drain regions on the fin active region at opposite sides of the gate structure, a first contact structure electrically connected to one of the source/drain regions, a pair of first contact block structures on opposite first sidewalls, respectively, of the first contact structure in the second direction.

Abstract: A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.

Abstract: A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

Abstract: A method is provided for fabricating a semiconductor device that includes: forming a gate pattern on a substrate; forming a source/drain in the vicinity of the gate pattern; forming an etch stop film, which covers the gate pattern and the source/drain, on the substrate; forming an interlayer insulating film on the etch stop film; forming a shared contact hole that exposes the gate pattern and the source/drain by etching the interlayer insulating film, wherein a polymer is generated in the shared contact hole a process of etching the interlayer insulating film; removing the polymer by performing etching using hydrogen gas, nitrogen gas or a mixture of hydrogen and nitrogen before etching the etch stop film; and etching the etch stop film.

Abstract: A method of forming a contact hole includes loading a substrate into a plasma chamber, the substrate including an etch stop layer, an insulation interlayer, a mask layer and a photoresist pattern sequentially disposed thereon, applying a DC voltage to an upper electrode and applying a first high frequency power and a second high frequency power to a lower electrode to generate plasma in the chamber, the first frequency power and second high frequency powers having different frequency levels, supplying a reaction gas to the chamber to etch the mask layer and the insulation interlayer, wherein the chamber is maintained at a temperature of 100° C. to 200° C.