Abstract: There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit description and ones of the plurality of HDL modules, the circuit netlist is responsible for defining behavioral relationships among associated ones of the HDL modules, and associate a timing-violation controller with the circuit netlist to ignore selected timing violations sensed as a function of various ones of the behavioral relationships during simulation of the desired circuit.

Abstract: An apparatus for and method of testing similar circuit blocks with test signals. The apparatus includes a first logic bus circuit, a second logic bus circuit, and a selector circuit. The first logic bus circuit is used to serially test the similar circuit blocks. The second logic bus circuit is used to concurrently test the similar circuit blocks. The selector circuit indicates an error with a high impedance circuit state. The number of output pins is dependent upon the number of test signals, not the number of similar circuit blocks. This allows the apparatus to be scalable to any number of similar circuit blocks without increasing the required number of output pins.