Patents by Inventor Hal Emmer

Hal Emmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260040648
    Abstract: A new semiconductor structure and method of fabrication is disclosed. The semiconductor structure includes a source-connected field plate, which in some embodiments, is located at least as close to the barrier layer as the gate field plate, if present. The source-connected field plate is formed by patterning the dielectric layer to create a cavity in which metal will be deposited to form the source-connected field plate. In some embodiments, there may be multiple source-connected field plates, which are each at a different distance from the barrier layer. These multiple source-connected field plates may be created using a single metal deposition process.
    Type: Application
    Filed: July 29, 2025
    Publication date: February 5, 2026
    Inventors: Hal Emmer, Sangmin Lee
  • Publication number: 20250301687
    Abstract: A new semiconductor structure is disclosed. The semiconductor structure includes an active region that is made narrower through the application of a p-type cap layer disposed thereupon. The p-type cap layer may be disposed on one side of the active region, or on both sides of the active region. This p-type cap layer may be applied to various semiconductor structures, including transistors, diodes and semiconductor resistors.
    Type: Application
    Filed: February 24, 2025
    Publication date: September 25, 2025
    Inventors: Hal Emmer, Bin Lu
  • Publication number: 20250159960
    Abstract: A new transistor structure for use with III-Nitride semiconductor structures is disclosed. The transistor includes heavily doped n++ layers located in the source region and the drain region. The source and drain electrodes are disposed on their respective heavily doped n++ layer. Further, in some embodiments, a portion of the gate electrode may be disposed on one or both of the heavily doped n++ regions. These regions improve the on-resistance of the transistor, especially for low voltage applications.
    Type: Application
    Filed: November 5, 2024
    Publication date: May 15, 2025
    Inventors: Dongfei Pei, Bin Lu, Hal Emmer, Mark Dipsey
  • Publication number: 20250022928
    Abstract: A technique for making contact to the cap layers in multifinger III-Nitride transistors with cap layers is described. A contact structure is disposed at an end of the transistor device and connects to the cap layer of individual fingers of the transistor device using a cap contact bus. A transistor is also described that includes a contact structure that is used to move the cap layer contact away from the individual fingers. Transistors may be created using unit cells, wherein each unit cell includes a contact structure and cap contact bus.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 16, 2025
    Inventor: Hal Emmer
  • Patent number: 11695052
    Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 4, 2023
    Assignee: Finwave Semiconductor, Inc.
    Inventors: Bin Lu, Dongfei Pei, Mark Dipsey, Hal Emmer
  • Publication number: 20210265477
    Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 26, 2021
    Inventors: Bin Lu, Dongfei Pei, Mark Dipsey, Hal Emmer
  • Publication number: 20160322514
    Abstract: Solar cells in accordance with a number of embodiments of the invention incorporate effectively transparent 3D contacts that redirect light incident on the contacts onto the photoabsorbing surfaces of the solar cells. One embodiment includes a photoabsorbing surface and a plurality of three-dimensional contacts formed on the photoabsorbing surface. The plurality of three-dimensional contacts are spaced apart so that radiation is incident on a portion of the photoabsorbing surface. In addition, the three-dimensional contacts include at least one surface that redirects radiation incident on the three-dimensional contacts onto the photoabsorbing surface.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 3, 2016
    Applicant: California Institute of Technology
    Inventors: Harry A. Atwater, Rebecca Saive, Aleca M. Borsuk, Hal Emmer, Colton Bukowsky, Sisir Yalamanchili