Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An apparatus and method for generating an elevated output voltage. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of a first phase and the second switch couples the second boot node to the output node during a first portion of a second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.

Abstract: An apparatus and method for generating an elevated output voltage. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of a first phase and the second switch couples the second boot node to the output node during a first portion of a second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An apparatus and method for generating an elevated output voltage. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of a first phase and the second switch couples the second boot node to the output node during a first portion of a second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.

Abstract: An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

Abstract: An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

Abstract: An internal voltage regulator for a synchronous random access memory “SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.