Patents by Inventor Halbert S. Lin

Halbert S. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9870812
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 16, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Publication number: 20170084324
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 9583169
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 28, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Patent number: 9569640
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 14, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • Patent number: 9552849
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 24, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S Lin
  • Publication number: 20160254040
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Publication number: 20160172019
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Patent number: 9361964
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 7, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Publication number: 20160104518
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 9311980
    Abstract: A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 12, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Patent number: 9230633
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 5, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S Lin
  • Patent number: 9230632
    Abstract: A word line driver circuit allows for dynamic selection of different word line voltages for selection and deselection of memory cells included in a resistive memory array in a manner that reduces circuit complexity, device count, and leakage currents.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: January 5, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Publication number: 20150356322
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 10, 2015
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • Patent number: 9135970
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 15, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • Publication number: 20150124524
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 7, 2015
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 9007811
    Abstract: A word line driver circuit allows for dynamic selection of different word line voltages for selection and deselection of memory cells included in a resistive memory array in a manner that reduces circuit complexity, device count, and leakage currents.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 8976610
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: March 10, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Publication number: 20140226396
    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 14, 2014
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Chitra K. Subramanian, Halbert S. Lin, Syed M. Alam, Thomas Andre
  • Publication number: 20140104937
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 17, 2014
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 6711068
    Abstract: A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: March 23, 2004
    Assignee: Motorola, Inc.
    Inventors: Chitra K. Subramanian, Brad J. Garni, Joseph J. Nahas, Halbert S. Lin, Thomas W. Andre