Patents by Inventor Haldane S. Henry
Haldane S. Henry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9564497Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: GrantFiled: June 24, 2015Date of Patent: February 7, 2017Assignee: Qorvo US, Inc.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Patent number: 9530853Abstract: A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 ?A/mm and around 50 ?A/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au).Type: GrantFiled: February 20, 2015Date of Patent: December 27, 2016Assignee: Qorvo US, Inc.Inventors: Haldane S. Henry, Eunki Hong, Charles S. Whitman
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Publication number: 20150295053Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Patent number: 9136341Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: GrantFiled: March 12, 2013Date of Patent: September 15, 2015Assignee: RF Micro Devices, Inc.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Publication number: 20150255560Abstract: A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 ?A/mm and around 50 ?A/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au).Type: ApplicationFiled: February 20, 2015Publication date: September 10, 2015Inventors: Haldane S. Henry, Eunki Hong, Charles S. Whitman
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Patent number: 9123645Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: November 21, 2013Date of Patent: September 1, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 9093420Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.Type: GrantFiled: March 12, 2013Date of Patent: July 28, 2015Assignee: RF Micro Devices, Inc.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Patent number: 9029986Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.Type: GrantFiled: May 25, 2012Date of Patent: May 12, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry
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Publication number: 20140087550Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: ApplicationFiled: November 21, 2013Publication date: March 27, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: BRUCE M. GREEN, HALDANE S. HENRY, CHUN-LI LIU, KAREN E. MOORE, MATTHIAS PASSLACK
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Patent number: 8592878Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: March 8, 2011Date of Patent: November 26, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Publication number: 20130277687Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: ApplicationFiled: March 12, 2013Publication date: October 24, 2013Applicant: RF MICRO DEVICES, INC.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Publication number: 20130280877Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.Type: ApplicationFiled: March 12, 2013Publication date: October 24, 2013Applicant: RF MICRO DEVICES, INC.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Publication number: 20130015462Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.Type: ApplicationFiled: May 25, 2012Publication date: January 17, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: BRUCE M. GREEN, HALDANE S. HENRY
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Patent number: 8193591Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).Type: GrantFiled: April 13, 2006Date of Patent: June 5, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry
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Publication number: 20110156051Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 7935620Abstract: Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: December 5, 2007Date of Patent: May 3, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Publication number: 20090146191Abstract: Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1).Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 6798064Abstract: An electronic component includes a substrate (110) and an airbridge (890) located over the substrate. The airbridge has at least a first layer and a second layer over the first layer. The airbridge is electrically conductive where the first layer of the airbridge is less resistive than the second layer of the airbridge.Type: GrantFiled: July 12, 2000Date of Patent: September 28, 2004Assignee: Motorola, Inc.Inventors: Haldane S. Henry, Darrell G. Hill, Colby G. Rampley
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Patent number: 6465297Abstract: A method of manufacturing a semiconductor component includes forming a first capacitor electrode (126) over a substrate (110), forming a capacitor dielectric layer (226) over the first capacitor electrode, and forming a second capacitor electrode (326) over the capacitor dielectric layer. The capacitor dielectric layer is made of aluminum.Type: GrantFiled: October 5, 2000Date of Patent: October 15, 2002Assignee: Motorola, Inc.Inventors: Haldane S. Henry, Darrell G. Hill, Jonathan K. Abrokwah, Mariam G. Sadaka