Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.

Abstract: A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and/or secondary gates are programmable.

Abstract: A semiconductor device includes a semiconductor substrate, a channel disposed over the semiconductor substrate and extending in a specific direction, a drain disposed at a first end of the channel, a source disposed at a second end of the channel, and a gate disposed over the channel and configured to control a current through the channel. The gate, or the channel, or both include a semiconductor material that is monocrystalline.

Abstract: A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and/or secondary gates are programmable.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a ferroelectric material. A structure of the disclosure may include a base over a substrate. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion. A ferroelectric spacer is adjacent the second portion of the base. Other structures include a ferroelectric layer over a back gate terminal of a substrate. A base is on the ferroelectric layer. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion.

Abstract: Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.

Abstract: Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.

Abstract: An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.

Abstract: The disclosure provides a structure with ferroelectric memory stacks having different switching voltages, and methods to provide the same. A structure of the disclosure includes a first ferroelectric memory stack over a substrate. The first ferroelectric memory stack has a first switching voltage. A second ferroelectric memory stack is serially coupled to the first ferroelectric memory stack over the substrate. The second ferroelectric memory stack has a second switching voltage, different from the first switching voltage.

Abstract: Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.

Abstract: Structures including a ferroelectric field-effect transistor and methods of forming a structure including a ferroelectric field-effect transistor. The structure comprises a semiconductor substrate, a semiconductor layer, a dielectric layer arranged between the semiconductor layer and the semiconductor substrate, and first and second wells in the semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. A ferroelectric field-effect transistor comprises a gate structure on the semiconductor layer over the first well and the second well. The gate structure includes a ferroelectric layer comprising a ferroelectric material.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: Structures including a ferroelectric field-effect transistor and methods of forming a structure including a ferroelectric field-effect transistor. The structure comprises a semiconductor substrate, a semiconductor layer, a dielectric layer arranged between the semiconductor layer and the semiconductor substrate, and first and second wells in the semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. A ferroelectric field-effect transistor comprises a gate structure on the semiconductor layer over the first well and the second well. The gate structure includes a ferroelectric layer comprising a ferroelectric material.

Abstract: Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.